Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration
Haque, Yusuf, Lewis, Donald E., Hales, Rex, Kier, Ryan J., Johancsik, Tracy, Watkins, Paul, Picken, William, Harper, Marcellus, Dujari, Shyam
Published in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (01.09.2014)
Published in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (01.09.2014)
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