Reducing process variation impact on replica-timed static random access memory sense timing
Desai, Nishith N., Haigh, Jonathan R., Clark, Lawrence T.
Published in Integration (Amsterdam) (01.09.2009)
Published in Integration (Amsterdam) (01.09.2009)
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Journal Article
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit
Haigh, J.R., Wilkerson, M.W., Miller, J.B., Beatty, T.S., Strazdus, S.J., Clark, L.T.
Published in IEEE journal of solid-state circuits (01.05.2005)
Published in IEEE journal of solid-state circuits (01.05.2005)
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Journal Article