A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking
KIM, Jung-Sik, CHI SUNG OH, RYU, Jang-Woo, PARK, Kiwon, SANG KYU KANG, KIM, So-Young, KIM, Hoyoung, BANG, Jong-Min, CHO, Hyunyoon, JANG, Minsoo, HAN, Cheolmin, LEE, Jung-Bae, LEE, Hocheol, JOO SUN CHOI, JUN, Young-Hyun, LEE, Donghyuk, HYONG RYOL HWANG, HWANG, Sooman, NA, Byongwook, MOON, Joungwook, KIM, Jin-Guk, PARK, Hanna
Published in IEEE journal of solid-state circuits (2012)
Published in IEEE journal of solid-state circuits (2012)
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Conference Proceeding
Journal Article
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques
Ha, Kyung-Soo, Lee, Seungseob, Park, Youn-Sik, Kwon, Hyuck-Joon, Oh, Tae-Young, Sohn, Young-Soo, Bae, Seung-Jun, Park, Kwang-Il, Lee, Jung-Bae, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Hwang, Hyong-Ryol, Park, Dukha, Kim, Young-Hwa, Son, Young Hoon, Na, Byongwook
Published in IEEE journal of solid-state circuits (01.01.2020)
Published in IEEE journal of solid-state circuits (01.01.2020)
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Journal Article
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Ha, Kyung-Soo, Lee, Chang-Kyo, Lee, Dongkeon, Moon, Daesik, Jang, Jin-Hun, Hwang, Hyong-Ryol, Chi, Hyungjoon, Park, Junghwan, Shin, Seungjun, Park, Dukha, Kim, Sang-Yun, Lim, Sukhyun, Park, Kiwon, Choi, YeonKyu, Kim, Young-Hwa, Son, Younghoon, Cho, Hyunyoon, Na, Byongwook, Ahn, Hyo-Joo, Lee, Seungseob, Choi, Seouk-Kyu, Park, Youn-Sik, Hyun, Seok-Hun, Chang, Soobong, Kwon, Hyuck-Joon, Choi, Jung-Hwan, Oh, Tae-Young, Sohn, Young-Soo, Park, Kwang-II, Jang, Seong-Jin
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
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Conference Proceeding
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking
Kim, Jung-Sik, Oh, Chi Sung, Lee, Hocheol, Lee, Donghyuk, Hwang, Hyong Ryol, Hwang, Sooman, Moon, Joungwook, Kim, Jin-Guk, Park, Hanna, Ryu, Jang-Woo, Park, Kiwon, Kang, Sang Kyu, Kim, So-Young, Kim, Hoyoung, Bang, Jong-Min, Cho, Hyunyoon, Jang, Minsoo, Han, Cheolmin, LeeLee, Jung-Bae, Choi, Joo Sun, Jun, Young-Hyun
Published in IEEE journal of solid-state circuits (01.01.2012)
Published in IEEE journal of solid-state circuits (01.01.2012)
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Journal Article
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Sujin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon-Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-Young Oh, In-Dal Song, Yong-Cheol Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01.02.2017)
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Conference Proceeding
Memory device having error correction function and operating method thereof
Park, Jung-Hwan, Chi, Hyung-Joon, Ha, Kyung-Soo, Oh, Tae-Young, Hwang, Hyong-Ryol
Year of Publication 10.05.2022
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Year of Publication 10.05.2022
Patent
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
Published in 2011 IEEE International Solid-State Circuits Conference (01.02.2011)
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Conference Proceeding
MEMORY DEVICE HAVING ERROR CORRECTION FUNCTION AND OPERATING METHOD THEREOF
Ha, Kyung-soo, Hwang, Hyong-ryol, Park, Jung-hwan, Oh, Tae-young, Chi, Hyung-joon
Year of Publication 24.10.2019
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Year of Publication 24.10.2019
Patent
Semiconductor memory device and memory system including the same
OH, TAE-YOUNG, HWANG, HYONG-RYOL, KIM, KI-HEUNG, LEE, KYUNG-HO, KIM, JONGOL
Year of Publication 01.03.2024
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Year of Publication 01.03.2024
Patent
Semiconductor memory device and memory system including the same
OH, TAE-YOUNG, HWANG, HYONG-RYOL, KIM, KI-HEUNG, LEE, KYUNG-HO, KIM, JONGOL
Year of Publication 01.02.2024
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Year of Publication 01.02.2024
Patent
Semiconductor memory device and memory system including the same
OH, TAE-YOUNG, HWANG, HYONG-RYOL, KIM, KI-HEUNG, LEE, KYUNG-HO, KIM, JONGOL
Year of Publication 01.01.2024
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Year of Publication 01.01.2024
Patent
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
LEE KYUNG-HO, KIM JONGUL, HWANG HYONG-RYOL, OH TAE-YOUNG, KIM KI-HEUNG
Year of Publication 29.12.2023
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Year of Publication 29.12.2023
Patent