A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
TU, Ming-Hsien, LIN, Jihi-Yu, CHUANG, Ching-Te, TSAI, Ming-Chien, LU, Chien-Yu, LIN, Yuh-Jiun, WANG, Meng-Hsueh, HUANG, Huan-Shun, LEE, Kuen-Di, SHIH, Wei-Chiang (willis), JOU, Shyh-Jye
Published in IEEE journal of solid-state circuits (01.06.2012)
Published in IEEE journal of solid-state circuits (01.06.2012)
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Journal Article
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
Wu, Shang-Lin, Li, Kuang-Yu, Huang, Po-Tsang, Hwang, Wei, Tu, Ming-Hsien, Lung, Sheng-Chi, Peng, Wei-Sheng, Huang, Huan-Shun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te
Published in IEEE transactions on circuits and systems. I, Regular papers (01.07.2017)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.07.2017)
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Journal Article
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Kan, Paul-Sen, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2015)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.05.2015)
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Journal Article
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
Chi-Shin Chang, Hao-i Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Kan, Paul-Sen, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
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Conference Proceeding
A 0.33-V, 500-kHz, 3.94- \mu\hbox 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
Lu, Chien-Yu, Tu, Ming-Hsien, Yang, Hao-I, Wu, Ya-Ping, Huang, Huan-Shun, Lin, Yuh-Jiun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te, Jou, Shyh-Jye, Hwang, Wei
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
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Journal Article
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsuan Chen, Yong-Jyun Hu, Kan, Paul-Sen, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
Published in 2014 27th IEEE International System-on-Chip Conference (SOCC) (01.09.2014)
Published in 2014 27th IEEE International System-on-Chip Conference (SOCC) (01.09.2014)
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Conference Proceeding
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control
Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Kan, Paul-Sen, Yong-Jyun Hu
Published in 2013 IEEE International SOC Conference (01.09.2013)
Published in 2013 IEEE International SOC Conference (01.09.2013)
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Conference Proceeding
A 0.33-V, 500-kHz, 3.94-[Formula Omitted] 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
Lu, Chien-Yu, Tu, Ming-Hsien, Yang, Hao-I, Wu, Ya-Ping, Huang, Huan-Shun, Lin, Yuh-Jiun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te, Jou, Shyh-Jye, Hwang, Wei
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.12.2012)
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Journal Article
A 0.35V, 375kHz, 5.43µW, 40nm, 128kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
Wu, Shang-Lin, Lu, Chien-Yu, Tu, Ming-Hsien, Huang, Huan-Shun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te
Published in Microelectronics (01.05.2016)
Published in Microelectronics (01.05.2016)
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Journal Article