A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET
Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny Cheng-Hsiang, Staszewski, Robert Bogdan
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
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Journal Article
3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from −25°C to 125°C
Lien, Bei-Shing, Liu, Szu Lin, Lai, Wei-Lin, Lu, Yi-Chen, Peng, Yung-Chow, Hsieh, Kenny Cheng-Hsiang
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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Conference Proceeding
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs
Savoj, Jafar, Hsieh, Kenny Cheng-Hsiang, Fu-Tai An, Gong, Jason, Jay Im, Xuewen Jiang, Jose, Anup P., Kireev, Vassili, Siok-Wei Lim, Roldan, Arianne, Turker, Didem Z., Upadhyaya, Parag, Wu, Daniel, Ken Chang
Published in IEEE journal of solid-state circuits (01.11.2013)
Published in IEEE journal of solid-state circuits (01.11.2013)
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Journal Article
Conference Proceeding
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET
Chen, Wei-Chih, Yang, Shu-Chun, Shih, Yu-Nan, Huang, Wen-Hung, Tsai, Chien-Chun, Hsieh, Kenny Cheng-Hsiang
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 7-nm 4-GHz Arm^1-Core-Based CoWoS^1 Chiplet Design for High-Performance Computing
Lin, Mu-Shan, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi
Published in IEEE journal of solid-state circuits (26.02.2020)
Published in IEEE journal of solid-state circuits (26.02.2020)
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Journal Article
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4
Lin, Mu-Shan, Tsai, Chien-Chun, Li, Shenggao, Huang, Tze-Chiang, Huang, Wen-Hung, Huang, Kate, Chen, Yu-Chi, Liu, Alex, Huang, Yu-Jie, Wang, Jimmy, Yang, Shu-Chun, Cheng, Nai-Chen, Li, Chao-Chieh, Kuo, Hsin-Hung, Chen, Wei-Chih, Wen, C.H., Lin, Kevin, Huang, Po-Yi, Hsieh, Kenny Cheng-Hsiang, Lee, Frank
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
Published in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (16.06.2024)
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Conference Proceeding