A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and −240.5-dB FoM in 7-nm FinFET
Tsai, Tsung-Hsien, Sheen, Ruey-Bin, Chang, Chih-Hsien, Hsieh, Kenny Cheng-Hsiang, Staszewski, Robert Bogdan
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
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Journal Article
3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from −25°C to 125°C
Lien, Bei-Shing, Liu, Szu Lin, Lai, Wei-Lin, Lu, Yi-Chen, Peng, Yung-Chow, Hsieh, Kenny Cheng-Hsiang
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
Published in 2024 IEEE International Solid-State Circuits Conference (ISSCC) (18.02.2024)
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Conference Proceeding
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Kenny Cheng-Hsiang, Chen, Ching-Fang, Huang, Wen-Hung, Hu, Chi-Wei, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank
Published in IEEE journal of solid-state circuits (01.04.2020)
Published in IEEE journal of solid-state circuits (01.04.2020)
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Journal Article
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing
Lin, Mu-Shan, Huang, Tze-Chiang, Tsai, Chien-Chun, Tam, King-Ho, Hsieh, Cheng-Hsiang, Chen, Tom, Huang, Wen-Hung, Hu, Jack, Chen, Yu-Chi, Goel, Sandeep Kumar, Fu, Chin-Ming, Rusu, Stefan, Li, Chao-Chieh, Yang, Sheng-Yao, Wong, Mei, Yang, Shu-Chun, Lee, Frank
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
Published in 2019 Symposium on VLSI Circuits (01.06.2019)
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Conference Proceeding
A 512×576 65-nm CMOS ISFET sensor for food safety screening with 123.8 mV/pH sensitivity and 0.01 pH resolution
Yu Jiang, Xu Liu, Tran Chien Dang, Mei Yan, Hao Yu, Jui-Cheng Huang, Cheng-Hsiang Hsieh, Tung-Tsun Chen
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Conference Proceeding
MULTI-TAP DECISION FEED-FORWARD EQUALIZER WITH PRECURSOR AND POSTCURSOR TAPS
PFAFF DIRK, ABBOTT ROB, PALUSA CHAITANYA, LAN PO HSIANG, HSIEH CHENG HSIANG, CHEN WEI LI
Year of Publication 11.08.2020
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Year of Publication 11.08.2020
Patent
CDR SerDes SERDES RECEIVER WITH OPTIMIZED CDR PULSE SHAPING
PFAFF DIRK, KUO FAN MING, ABBOTT ROB, RAMIREZ ROLANDO, PALUSA CHAITANYA, HSIEH CHENG HSIANG, CHEN WEI LI
Year of Publication 11.08.2020
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Year of Publication 11.08.2020
Patent
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs
Savoj, Jafar, Hsieh, Kenny Cheng-Hsiang, Fu-Tai An, Gong, Jason, Jay Im, Xuewen Jiang, Jose, Anup P., Kireev, Vassili, Siok-Wei Lim, Roldan, Arianne, Turker, Didem Z., Upadhyaya, Parag, Wu, Daniel, Ken Chang
Published in IEEE journal of solid-state circuits (01.11.2013)
Published in IEEE journal of solid-state circuits (01.11.2013)
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Journal Article
Conference Proceeding