High-Speed Architectures for Multiplication Using Reordered Normal Basis
Hosseinzadeh Namin, Ashkan H., Huapeng Wu, Ahmadi, M.
Published in IEEE transactions on computers (01.02.2012)
Published in IEEE transactions on computers (01.02.2012)
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Journal Article
A Word-Level Finite Field Multiplier Using Normal Basis
Namin, Ashkan Hosseinzadeh, Huapeng Wu, Ahmadi, Majid
Published in IEEE transactions on computers (01.06.2011)
Published in IEEE transactions on computers (01.06.2011)
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Journal Article
프로세싱 유닛에서의 워크로드 기반 클록 조정
NIJASURE MANGESH P, REGNIERE LOUIS, HOSSEINZADEH NAMIN ASHKAN, MANTOR MICHAEL
Year of Publication 26.07.2022
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Year of Publication 26.07.2022
Patent
Improved Area-Time Trade-offs for Field Multiplication using Optimal Normal Bases
Adikari, Jithra, Barsoum, Ayad, Hasan, Anwar, Namin, Ashkan Hosseinzadeh, Negre, Christophe
Published in IEEE transactions on computers (01.01.2013)
Published in IEEE transactions on computers (01.01.2013)
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Journal Article
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials
Hasan, M. A., Namin, A. H., Negre, C.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2012)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.2012)
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Journal Article
Efficient hardware implementation of the hyperbolic tangent sigmoid function
Namin, A.H., Leboeuf, K., Muscedere, R., Huapeng Wu, Ahmadi, M.
Published in 2009 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2009)
Published in 2009 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2009)
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Conference Proceeding
Graphics processing units with power management and latency reduction
Hosseinzadeh Namin, Ashkan, Jin, Seunghun, Tan, Teik-Chung, Godey, Sreekanth
Year of Publication 02.01.2024
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Year of Publication 02.01.2024
Patent
WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT
REGNIERE, Louis, NIJASURE, Mangesh P, HOSSEINZADEH NAMIN, Ashkan, MANTOR, Michael
Year of Publication 27.12.2023
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Year of Publication 27.12.2023
Patent
A high speed word level finite field multiplier using reordered normal basis
Namin, Ashkan Hosseinzadeh, Huapeng Wu, Ahmadi, Majid
Published in 2008 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2008)
Published in 2008 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2008)
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Conference Proceeding
Reducing save restore latency for power control based on write signals
Hosseinzadeh Namin, Ashkan, Acharya, Anirudh R, Ashkar, Alexander Fuad
Year of Publication 14.02.2023
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Year of Publication 14.02.2023
Patent
WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT
REGNIERE, Louis, NIJASURE, Mangesh P, HOSSEINZADEH NAMIN, Ashkan, MANTOR, Michael
Year of Publication 28.09.2022
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Year of Publication 28.09.2022
Patent
GRAPHICS PROCESSING UNITS WITH POWER MANAGEMENT AND LATENCY REDUCTION
TAN, Teik-Chung, HOSSEINZADEH NAMIN, Ashkan, JIN, Seunghun, GODEY, Sreekanth
Year of Publication 30.06.2022
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Year of Publication 30.06.2022
Patent
Workload-based clock adjustment at a processing unit
Hosseinzadeh Namin, Ashkan, Mantor, Michael, Regniere, Louis, Nijasure, Mangesh P
Year of Publication 01.03.2022
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Year of Publication 01.03.2022
Patent
REDUCING SAVE RESTORE LATENCY FOR POWER CONTROL
ASHKAR, Alexander Fuad, HOSSEINZADEH NAMIN, Ashkan, ACHARYA, Anirudh R
Year of Publication 10.02.2022
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Year of Publication 10.02.2022
Patent
Efficient VLSI implementation of a finite field multiplier using reordered normal basis
Leboeuf, K, Namin, A H, Huapeng Wu, Muscedere, R, Ahmadi, M
Published in 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (01.08.2010)
Published in 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (01.08.2010)
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Conference Proceeding
WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT
REGNIERE, Louis, NIJASURE, Mangesh P, HOSSEINZADEH NAMIN, Ashkan, MANTOR, Michael
Year of Publication 27.05.2021
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Year of Publication 27.05.2021
Patent