Universal Testing for Linear Feed-Forward/Feedback Shift Registers
FUJIWARA, Hideo, FUJIWARA, Katsuya, HOSOKAWA, Toshinori
Published in IEICE Transactions on Information and Systems (01.05.2020)
Published in IEICE Transactions on Information and Systems (01.05.2020)
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Journal Article
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions
Yoshimura, Masayoshi, Takahashi, Yoshiyasu, Yamazaki, Hiroshi, Hosokawa, Toshinori
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
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Conference Proceeding
Journal Article
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation
Masuda, Tetsuya, Nishimaki, Jun, Hosokawa, Toshinori, Fujiwara, Hideo
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
Published in 2015 IEEE 24th Asian Test Symposium (ATS) (01.11.2015)
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Conference Proceeding
Journal Article
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns
Hosokawa, Toshinori, Yamazaki, Hiroshi, Takeda, Shun, Yoshimura, Masayoshi
Published in 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) (01.07.2018)
Published in 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) (01.07.2018)
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Conference Proceeding
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT
Asami, Ryuki, Hosokawa, Toshinori, Yoshimura, Masayoshi, Arai, Masayuki
Published in 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (19.10.2020)
Published in 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (19.10.2020)
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Conference Proceeding
Test point insertion methods to reduce the number of ATPG patterns
Yoshimura, Masayoshi, Hosokawa, Toshinori, Ohta, Misuyasu
Published in Electronics & communications in Japan. Part 2, Electronics (01.05.2006)
Published in Electronics & communications in Japan. Part 2, Electronics (01.05.2006)
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Journal Article
A State Assignment Method to Improve Transition Fault Coverage for Controllers
Yoshimura, Masayoshi, Takeuchi, Yuki, Yamazaki, Hiroshi, Hosokawa, Toshinori
Published in 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2019)
Published in 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2019)
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Conference Proceeding
A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively
Hosokawa, Toshinori, Yamazaki, Hiroshi, Misawa, Kenichiro, Yoshimura, Masayoshi, Hirama, Yuki, Arai, Masavuki, Arai, Masayuki
Published in 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2019)
Published in 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2019)
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Conference Proceeding
A dynamic test compaction method on low power test generation based on capture safe test vectors
Hosokawa, Toshinori, Hirai, Atsushi, Yamazaki, Hiroshi, Arai, Masayuki
Published in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2017)
Published in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (01.10.2017)
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Conference Proceeding
Evaluation of transition untestable faults using a multi-cycle capture test generation method
Yoshimura, Masayoshi, Ogawa, Hiroshi, Hosokawa, Toshinori, Yamazaki, Koji
Published in 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (01.04.2010)
Published in 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (01.04.2010)
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Conference Proceeding
A test pattern matching method on bast architecture using don't care identification for random pattern resistant faults
Hosokawa, T, Yun Chen, LingLing Wan, Wakazono, M, Yoshimura, M
Published in 2010 10th International Symposium on Communications and Information Technologies (01.10.2010)
Published in 2010 10th International Symposium on Communications and Information Technologies (01.10.2010)
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Conference Proceeding
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers
Hosokawa, Toshinori, Iizuka, Kyohei, Yoshimura, Masayoshi
Published in 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (03.10.2023)
Published in 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (03.10.2023)
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Conference Proceeding