Search Results - "HIDEKI SHOYAMA" :: K.UTB vyhledávací portál

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Logic circuit delay restriction generation processing apparatus for logic synthesis, allocates delay restriction value to each hierarchy of logic circuit and outputs to memory for logic synthesis

by SHOYAMA, HIDEKI
Year of Publication 07.09.2000

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Solid-state image pickup device, semiconductor device, and camera system

by SHOYAMA HIDEKI
Year of Publication 26.05.2010

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DEVICE AND METHOD FOR GENERATING AND PROCESSING RESTRICTION FOR LOGICAL SYNTHESIS

by SHOYAMA HIDEKI
Year of Publication 04.08.2000

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TWI645707B

by IKEDA, YUSUKE, UDOU, YUUICHI, SAKAMOTO, YOSHIMASA, SHOYAMA, HIDEKI, KUMAGAI, OICHI
Year of Publication 21.12.2018

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TWI636558B

by UDOU, YUUICHI, IKEDA, YUSUKE, SAKAMOTO, YOSHIMASA, SHOYAMA, HIDEKI, KUMAGAI, OICHI
Year of Publication 21.09.2018

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TWI521965B

by KAWAGUCHI, SHUNJI, SHOYAMA, HIDEKI, HIROTA, ISAO
Year of Publication 11.02.2016

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SOLID-STATE IMAGE CAPTURE ELEMENT AND ELECTRONIC DEVICE

by IKEDA YUSUKE, UDOU YUUICHI, SAKAMOTO YOSHIMASA, KUMAGAI OICHI, SHOYAMA HIDEKI
Year of Publication 11.05.2016

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Imaging device and imaging method, electronic apparatus, as well as program

by KAWAGUCHI, SHUNJI, SHOYAMA, HIDEKI, HIROTA, ISAO
Year of Publication 16.12.2013

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Solid-state image capture element and electronic device

by IKEDA, YUSUKE, UDOU, YUUICHI, SAKAMOTO, YOSHIMASA, SHOYAMA, HIDEKI, KUMAGAI, OICHI
Year of Publication 16.06.2015

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Electronic device and image sensor

by UDOU, YUUICHI, IKEDA, YUSUKE, SAKAMOTO, YOSHIMASA, SHOYAMA, HIDEKI, KUMAGAI, OICHI
Year of Publication 16.03.2015

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