A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer
Hidaka, Yasuo, Gai, Weixin, Hattori, Akira, Horie, Takeshi, Jiang, Jian, Kanda, Kouichi, Koyanagi, Yoichi, Matsubara, Satoshi, Osone, Hideki
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
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