Shape of error surfaces in SpikeProp
Fujita, Masaru, Takase, Haruhiko, Kita, Hidehiko, Hayashi, Terumine
Published in 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) (01.06.2008)
Published in 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) (01.06.2008)
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Conference Proceeding
Journal Article
On Test Data Compression Using Selective Don’t-Care Identification
Hayashi, Terumine, Yoshioka, Haruna, Shinogi, Tsuyoshi, Kita, Hidehiko, Takase, Haruhiko
Published in Journal of computer science and technology (01.03.2005)
Published in Journal of computer science and technology (01.03.2005)
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Journal Article
On Test Data Compression Using Selective Don?t-Care Identification
Hayashi, Terumine, Yoshioka, Haruna, Shinogi, Tsuyoshi, Kita, Hidehiko, Takase, Haruhiko
Published in Journal of computer science and technology (01.03.2005)
Published in Journal of computer science and technology (01.03.2005)
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Journal Article
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing
Hayashi, T., Ikeda, N., Shinogi, T., Takase, H., Kita, H.
Published in 2006 15th Asian Test Symposium (01.11.2006)
Published in 2006 15th Asian Test Symposium (01.11.2006)
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Conference Proceeding
Faulty resistance sectioning technique for resistive bridging fault ATPG systems
Shinogi, T., Kanbayashi, T., Yoshikawa, T., Tsuruoka, S., Hayashi, T.
Published in Proceedings - Asian Test Symposium (2001)
Published in Proceedings - Asian Test Symposium (2001)
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Conference Proceeding
Journal Article
Cyclic greedy generation method for limited number of IDDQ tests
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Conference Proceeding
Journal Article
Obstacle to training SpikeProp networks - Cause of surges in training process
Takase, H., Fujita, M., Kawanaka, H., Tsuruoka, S., Kita, H., Hayashi, T.
Published in 2009 International Joint Conference on Neural Networks (01.06.2009)
Published in 2009 International Joint Conference on Neural Networks (01.06.2009)
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Conference Proceeding
Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing
Shinogi, T., Arakawa, K., Hayashi, T.
Published in 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era (01.04.2009)
Published in 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era (01.04.2009)
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Conference Proceeding
Enhancing both generalization and fault tolerance of multilayer neural networks
Haruhiko, T., Masahiko, M., Hidehiko, K., Terumine, H.
Published in 2007 International Joint Conference on Neural Networks (01.08.2007)
Published in 2007 International Joint Conference on Neural Networks (01.08.2007)
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Conference Proceeding
Test data compression technique using selective don't-care identification
Hayashi, Terumine, Yoshioka, Haruna, Shinogi, Tsuyoshi, Kita, Hidehiko, Takase, Haruhiko
Published in Proceedings of the 2004 Asia and South Pacific Design Automation Conference (27.01.2004)
Published in Proceedings of the 2004 Asia and South Pacific Design Automation Conference (27.01.2004)
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Conference Proceeding
Test data compression technique using selective don't-care identification
Hayashi, Terumine, Yoshioka, Haruna, Shinogi, Tsuyoshi, Kita, Hidehiko, Takase, Haruhiko
Published in with EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair; 27-30 Jan. 2004 (01.01.2004)
Published in with EDA Technofair Design Automation Conference Asia and South Pacific: Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair; 27-30 Jan. 2004 (01.01.2004)
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Conference Proceeding