Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact
Zhen Fang, Hallnor, Erik G, Bin Li, Leddige, Michael, Donglai Dai, Seung Eun Lee, Makineni, Srihari, Iyer, Ravi
Published in IEEE computer architecture letters (01.02.2010)
Published in IEEE computer architecture letters (01.02.2010)
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Journal Article
SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
FAHIM BAHAA, CHAMBERLAIN JEFFREY D, VAN DOREN STEPHEN R, JUAN ANTONIO, LIU YEN CHENG, HALLNOR ERIK G
Year of Publication 18.04.2016
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Year of Publication 18.04.2016
Patent
A unified compressed memory hierarchy
Hallnor, E.G., Reinhardt, S.K.
Published in 11th International Symposium on High-Performance Computer Architecture (2005)
Published in 11th International Symposium on High-Performance Computer Architecture (2005)
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Conference Proceeding
A fully associative software-managed cache design
Hallnor, Erik G, Reinhardt, Steven K
Published in Proceedings of the 27th annual International Symposium on Computer Architecture (01.05.2000)
Published in Proceedings of the 27th annual International Symposium on Computer Architecture (01.05.2000)
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Journal Article
MASKING A POWER STATE OF A CORE OF A PROCESSOR
Mulla, Dean, Choubal, Ashish V, Garg, Vivek, Hallnor, Erik G, Novakovsky, Larisa, Sistla, Krishnakanth V, Gendler, Alexander, Weier, Kimberly C
Year of Publication 06.11.2024
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Year of Publication 06.11.2024
Patent
MASKING A POWER STATE OF A CORE OF A PROCESSOR
SISTLA, Krishnakanth V, HALLNOR, Erik G, WEIER, Kimberly C, GARG, Vivek, MULLA, Dean, CHOUBAL, Ashish V, GENDLER, Alexander, NOVAKOVSKY, Larisa
Year of Publication 17.05.2023
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Year of Publication 17.05.2023
Patent
MASKING A POWER STATE OF A CORE OF A PROCESSOR
Mulla, Dean, Choubal, Ashish V, Garg, Vivek, Hallnor, Erik G, Novakovsky, Larisa, Sistla, Krishnakanth V, Gendler, Alexander, Weier, Kimberly C
Year of Publication 15.06.2022
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Year of Publication 15.06.2022
Patent
SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS
LIU, Yen-Cheng, FAHIM, Bahaa, HALLNOR, Erik G, CHAMBERLAIN, Jeffrey D, VAN DOREN, Stephen R, JUAN, Antonio
Year of Publication 05.05.2021
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Year of Publication 05.05.2021
Patent
Scalably mechanism to implement an instruction that monitors for writes to an address
Van Doren, Stephen R, Chamberlain, Jeffrey D, Fahim, Bahaa, Hallnor, Erik G, Juan, Antonio, Liu, Yen-Cheng
Year of Publication 07.07.2020
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Year of Publication 07.07.2020
Patent
POWER MANAGEMENT IN AN UNCORE FABRIC
SHRALL, Jeremy J, NAGARAJAN, Ramadass, HARRINGTON, Ezra N, HALLNOR, Erik G, ABRAHAM, Vinit Mathew
Year of Publication 08.08.2018
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Year of Publication 08.08.2018
Patent
Shared flow control credits
Adler, Robert P, Hallnor, Erik G, Toepfer, Robert J, Theobald, Kevin B, Vakharwala, Rupin H
Year of Publication 24.04.2018
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Year of Publication 24.04.2018
Patent
MASKING A POWER STATE OF A CORE OF A PROCESSOR
SISTLA, Krishnakanth V, HALLNOR, Erik G, WEIER, Kimberly C, GARG, Vivek, MULLA, Dean, CHOUBAL, Ashish V, GENDLER, Alexander, NOVAKOVSKY, Larisa
Year of Publication 03.04.2019
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Year of Publication 03.04.2019
Patent
POWER MANAGEMENT IN AN UNCORE FABRIC
SHRALL, Jeremy J, NAGARAJAN, Ramadass, HARRINGTON, Ezra N, HALLNOR, Erik G, ABRAHAM, Vinit Mathew
Year of Publication 01.11.2017
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Year of Publication 01.11.2017
Patent