Many-Core vs. Many-Thread Machines: Stay Away From the Valley
Guz, Zvika, Bolotin, Evgeny, Keidar, Idit, Kolodny, Avinoam, Mendelson, Avi, Weiser, Uri C.
Published in IEEE computer architecture letters (01.01.2009)
Published in IEEE computer architecture letters (01.01.2009)
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Journal Article
Efficient Link Capacity and QoS Design for Network-on-Chip
Guz, Z., Walter, I., Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.
Published in Proceedings of the Design Automation & Test in Europe Conference (2006)
Published in Proceedings of the Design Automation & Test in Europe Conference (2006)
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Conference Proceeding
Nahalal: Cache Organization for Chip Multiprocessors
Guz, Z., Keidar, I., Kolodny, A., Weiser, U.C.
Published in IEEE computer architecture letters (01.01.2007)
Published in IEEE computer architecture letters (01.01.2007)
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Journal Article
Threads vs. caches: Modeling the behavior of parallel workloads
Guz, Z, Itzhak, O, Keidar, I, Kolodny, A, Mendelson, A, Weiser, U C
Published in 2010 IEEE International Conference on Computer Design (01.10.2010)
Published in 2010 IEEE International Conference on Computer Design (01.10.2010)
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Conference Proceeding
The Power of Priority: NoC Based Distributed Cache Coherency
Bolotin, E., Guz, Z., Cidon, I., Ginosar, R., Kolodny, A.
Published in First International Symposium on Networks-on-Chip (NOCS'07) (01.05.2007)
Published in First International Symposium on Networks-on-Chip (NOCS'07) (01.05.2007)
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Conference Proceeding