A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
Kirihata, T., Mueller, G., Ji, B., Frankowsky, G., Ross, J.M., Terletzki, H., Netis, D.G., Weinfurtner, O., Hanson, D.R., Daniel, G., Hsu, L.L.-C., Sotraska, D.W., Reith, A.M., Hug, M.A., Guay, K.P., Selz, M., Poechmueller, P., Hoenigschmid, H., Wordeman, M.R.
Published in IEEE journal of solid-state circuits (01.11.1999)
Published in IEEE journal of solid-state circuits (01.11.1999)
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Journal Article
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H, Frey, A, DeBrosse, J.K, Kirihata, T, Mueller, G, Storaska, D.W, Daniel, G, Frankowsky, G, Guay, K.P, Hanson, D.R, Hsu, L.L.-C, Ji, B, Netis, D.G, Panaroni, S, Radens, C, Reith, A.M, Terletzki, H, Weinfurtner, O, Alsmeier, J, Weber, W, Wordeman, M.R
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
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Journal Article
A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
Hoenigschmid, H., Frey, A., DeBrosse, J.K., Kirihata, T., Mueller, G., Storaska, D.W., Daniel, G., Frankowsky, G., Guay, K.P., Hanson, D.R., Hsu, L.L.-C., Ji, B., Netis, D.G., Panaroni, S., Radens, C., Reith, A.M., Terletzki, H., Weinfurtner, O., Alsmeier, J., Weber, W., Wordeman, M.R.
Published in IEEE journal of solid-state circuits (01.05.2000)
Published in IEEE journal of solid-state circuits (01.05.2000)
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Journal Article