A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications
Yin, Shouyi, Ouyang, Peng, Tang, Shibin, Tu, Fengbin, Li, Xiudong, Zheng, Shixuan, Lu, Tianyi, Gu, Jiangyuan, Liu, Leibo, Wei, Shaojun
Published in IEEE journal of solid-state circuits (01.04.2018)
Published in IEEE journal of solid-state circuits (01.04.2018)
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Journal Article
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory
Yin, Shouyi, Yao, Xianqing, Lu, Tianyi, Liu, Dajiang, Gu, Jiangyuan, Liu, Leibo, Wei, Shaojun
Published in IEEE transactions on parallel and distributed systems (01.09.2017)
Published in IEEE transactions on parallel and distributed systems (01.09.2017)
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Journal Article
Stress-aware loops mapping on CGRAs with considering NBTI aging effect
Jiangyuan Gu, Shouyi Yin, Shaojun Wei
Published in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2017)
Published in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (01.06.2017)
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Conference Proceeding
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration
Gu, Jiangyuan, Yin, Shouyi, Liu, Leibo, Wei, Shaojun
Published in IEEE transactions on parallel and distributed systems (01.09.2018)
Published in IEEE transactions on parallel and distributed systems (01.09.2018)
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Journal Article
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation
Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
Published in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2017)
Published in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) (01.01.2017)
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Conference Proceeding
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA
Kou, Mingyang, Gu, Jiangyuan, Wei, Shaojun, Yao, Hailong, Yin, Shouyi
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
Published in 2020 57th ACM/IEEE Design Automation Conference (DAC) (01.07.2020)
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Conference Proceeding
Joint Modulo Scheduling and [Formula Omitted] Assignment for Loop Mapping on Dual-[Formula Omitted] CGRAs
Yin, Shouyi, Gu, Jiangyuan, Liu, Dajiang, Liu, Leibo, Wei, Shaojun
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.09.2016)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.09.2016)
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Journal Article
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA
Wu, Qidie, Gu, Jiangyuan, Lin, Youxu, Han, Boxiao, He, Hongjun, Hu, Yang, Liu, Leibo, Wei, Shaojun, Yin, Shouyi
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)
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Conference Proceeding
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow
Hui, Haojia, Gu, Jiangyuan, Hu, Xunbo, Hu, Yang, Liu, Leibo, Wei, Shaojun, Yin, Shouyi
Year of Publication 03.09.2023
Year of Publication 03.09.2023
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Journal Article
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating
Zhang, Song, Gu, Jiangyuan, Yin, Shouyi, Liu, Leibo, Wei, Shaojun
Published in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (18.01.2021)
Published in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (18.01.2021)
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Conference Proceeding
Efficient and Flexible Implementation of FFT Application for CGRA Processor
Yi, Yashuang, Gu, Jiangyuan, Luo, Lie, Wang, Zhi, Han, Boxiao, He, Hongjun, Yin, Shouyi
Published in 2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP) (21.04.2023)
Published in 2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP) (21.04.2023)
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Conference Proceeding
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs
Li, Cheng, Gu, Jiangyuan, Yin, Shouyi, Liu, Leibo, Wei, Shaojun
Published in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (18.01.2021)
Published in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC) (18.01.2021)
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Conference Proceeding
A Reconfigurable 2D-Mesh NoC Design with Agile Development Technique of SpinalHDL
Ding, Chen, Gu, Jiangyuan, Du, Yi, Han, Boxiao, He, Hongjun, Hu, Yang, Liu, Leibo, Wei, Shaojun, Yin, Shouyi
Published in 2023 International Symposium of Electronics Design Automation (ISEDA) (08.05.2023)
Published in 2023 International Symposium of Electronics Design Automation (ISEDA) (08.05.2023)
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Conference Proceeding
MSAM: A Multi-Layer Bi-LSTM Based Speech to Vector Model with Residual Attention Mechanism
Cui, Dongdong, Yin, Shouyi, Gu, Jiangyuan, Liu, Leibo, Wei, Shaojun
Published in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) (01.06.2019)
Published in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) (01.06.2019)
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Conference Proceeding
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow
Haojia Hui, Gu, Jiangyuan, Hu, Xunbo, Hu, Yang, Liu, Leibo, Wei, Shaojun, Yin, Shouyi
Published in arXiv.org (03.09.2023)
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Published in arXiv.org (03.09.2023)
Paper
Decentralized multi-PEA architecture CGRA reconfigurable processor
WU QIDIE, HAN HUIMING, GU JIANGYUAN, YIN SHOUYI, WEI SHAOJUN, HU XUNBO
Year of Publication 08.03.2024
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Year of Publication 08.03.2024
Patent