A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node
Klostermann, U.K., Angerbauer, M., Gruning, U., Kreupl, F., Ruhrig, M., Dahmani, F., Kund, M., Muller, G.
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
Published in 2007 IEEE International Electron Devices Meeting (01.12.2007)
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Conference Proceeding
Gate prespacers for high density DRAMs
Divakaruni, R., Weybright, M., Li, Y., Gruening, U., Mandelman, J., Gambino, J., Alsmeier, J., Bronner, G.
Published in 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) (1999)
Published in 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) (1999)
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Conference Proceeding
A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
Radens, C.J., Gruening, U., Weybright, M.E., DeBrosse, J.K., Kleinhenz, R.L., Hoenigschmid, H., Thomas, A.C., Mandelman, J.A., Alsmeier, J., Bronner, G.B.
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
Published in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) (1998)
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A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM
Radens, C.J., Gruening, U., Mandelman, J.A., Seitz, M., Lea, D., Casarotto, D., Clevenger, L., Nesbit, L., Malik, R., Halle, S., Kudelka, S., Tews, H., Divakaruni, R., Sim, J., Strong, A., Tibbel, D., Arnold, N., Bukofsky, S., Preuninger, J., Kunkel, G., Bronner, G.
Published in 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) (2000)
Published in 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104) (2000)
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An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM
Radens, C.J., Kudelka, S., Nesbit, L., Malik, R., Dyer, T., Dubuc, C., Joseph, T., Seitz, M., Clevenger, L., Arnold, N., Mandelman, J., Divakaruni, R., Casarotto, D., Lea, D., Jaiprakash, V.C., Sim, J., Faltermeier, J., Low, K., Strane, J., Halle, S., Ye, Q., Bukofsky, S., Gruening, U., Schloesser, T., Bronner, G.
Published in International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) (2000)
Published in International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138) (2000)
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A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb
Gruening, U., Radens, C.J., Mandelman, J.A., Michaelis, A., Seitz, M., Arnold, N., Lea, D., Casarotto, D., Knorr, A., Halle, S., Ivers, T.H., Economikos, L., Kudelka, S., Rahn, S., Tews, H., Lee, H., Divakaruni, R., Welser, J.J., Furukawa, T., Kanarsky, T.S., Alsmeier, J., Bronner, G.B.
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
Published in International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) (1999)
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COMPOSICION DE MALLA QUE COMPRENDE UN COMPONENTE DE MONOMEROS MULTIFUNCIONALES, UN COMPONENTE SACARIDO, DONDE EL COMPONENTE MONOMERO Y EL COMPONENTE SACARIDO SE PONEN EN CONTACTO EN PRESENCIA DE UNA COMPOSICION SOLVENTE; PROCEDIMIENTO PARA PREPARAR D
TOM SCHOTTMAN; JOSEPH CONTE; ZICHUN LU; XIN QU; RAINER GRUENING; ZHENG WANG; KAREN MERRIT; PAUL N. CHEN; PAAQUALE P. VIC
Year of Publication 20.06.2008
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Year of Publication 20.06.2008
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