VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
Sarangi, S.R., Greskamp, B., Teodorescu, R., Nakano, J., Tiwari, A., Torrellas, J.
Published in IEEE transactions on semiconductor manufacturing (01.02.2008)
Published in IEEE transactions on semiconductor manufacturing (01.02.2008)
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Journal Article
Conference Proceeding
EVAL: Utilizing processors with variation-induced timing errors
Sarangi, Smruti, Greskamp, Brian, Tiwari, Abhishek, Torrellas, Josep
Published in 2008 41st IEEE/ACM International Symposium on Microarchitecture (08.11.2008)
Published in 2008 41st IEEE/ACM International Symposium on Microarchitecture (08.11.2008)
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Conference Proceeding
The BubbleWrap many-core: popping cores for sequential acceleration
Karpuzcu, Ulya R., Greskamp, Brian, Torrellas, Josep
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12.12.2009)
Published in 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (12.12.2009)
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Conference Proceeding
A virtual machine for merit-based runtime reconfiguration
Greskamp, B., Sass, R.
Published in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) (2005)
Published in 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) (2005)
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Conference Proceeding
Blueshift: Designing processors for timing speculation from the ground up
Greskamp, B., Lu Wan, Karpuzcu, U.R., Cook, J.J., Torrellas, J., Deming Chen, Zilles, C.
Published in 2009 IEEE 15th International Symposium on High Performance Computer Architecture (01.02.2009)
Published in 2009 IEEE 15th International Symposium on High Performance Computer Architecture (01.02.2009)
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Conference Proceeding
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
Sarangi, S.R., Greskamp, B., Torrellas, J.
Published in International Conference on Dependable Systems and Networks (DSN'06) (2006)
Published in International Conference on Dependable Systems and Networks (DSN'06) (2006)
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Conference Proceeding
A Model for Timing Errors in Processors with Parameter Variation
Sarangi, S.R., Greskamp, B., Torrellas, J.
Published in 8th International Symposium on Quality Electronic Design (ISQED'07) (01.03.2007)
Published in 8th International Symposium on Quality Electronic Design (ISQED'07) (01.03.2007)
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Conference Proceeding