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Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

by Boyer, Marc, Graillat, Amaury, Dupont de Dinechin, Benoît, Migge, Jörn
Published in Performance evaluation (01.11.2020)

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Journal Article

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Parallel code generation of synchronous programs for a many-core architecture

by Graillat, Amaury, Moy, Matthieu, Raymond, Pascal, de Dinechin, Benoit Dupont
Published in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2018)

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Conference Proceeding

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Parallel code generation of synchronous programs for a many-core architecture

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