A New Combined Methodology for Write-Margin Extraction of Advanced SRAM
Gierczynski, N., Borot, B., Planes, N., Brut, H.
Published in 2007 IEEE International Conference on Microelectronic Test Structures (01.03.2007)
Published in 2007 IEEE International Conference on Microelectronic Test Structures (01.03.2007)
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Conference Proceeding
On the 6T-SRAM Cells Degradation Characterization in Ultra-Scaled CMOS Technologies
Nowak, E., Denais, M., Gierczynski, N.
Published in 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual (01.04.2007)
Published in 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual (01.04.2007)
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Conference Proceeding
0.525/spl mu/m/sup 2/ 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers
Vandooren, A., Hobbs, C., Faynot, O., Perreau, P., Denorme, S., Fenouillet-Beranger, C., Gallon, C., Morin, C., Zauner, A., lmbert, G., Bernard, H., Garnier, P., Gabette, L., Broekaart, M., Aminpur, M., Barnola, S., Loubet, N., Dutartre, D., Korman, T., Chabanne, G., Martin, F., Le Tiec, Y., Gierczynski, N., Smith, S., Laviron, C., Bidaud, M., Pouilloux, I., Bensahel, D., Skotnicki, T., Mingam, H., Wild, A.
Published in 2005 IEEE International SOI Conference Proceedings (2005)
Published in 2005 IEEE International SOI Conference Proceedings (2005)
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Conference Proceeding
0.248/spl mu/m/sup 2/ and 0.334/spl mu/m/sup 2/ conventional bulk 6T-SRAM bit-cells for 45nm node low cost - general purpose applications
Boeuf, F., Arnaud, F., Boccaccio, C., Salvetti, F., Todeschini, J., Pain, L., Jurdit, M., Manakli, S., Icard, B., Planes, N., Gierczynski, N., Denorme, S., Borot, B., Ortolland, C., Duriez, B., Tavel, B., Gouraud, P., Broekaart, M., Dejonghe, V., Brun, P., Guyader, F., Morini, P., Reddy, C., Aminpur, M., Laviron, C., Smith, S., Jacquemin, J.P., Mellier, M., Andre, F., Bicais-Lepinay, N., Jullian, S., Bustos, J., Skotnicki, T.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction
Muller, M., Mondot, A., Gierczynski, N., Aime, D., Froment, B., Leverd, F., Gouraud, P., Talbot, A., Descombes, S., Morand, Y., Le Tiec, Y., Besson, P., Toffoli, A., Ribes, G., Roux, J.-M., Pokrant, S., Andre, F., Skotnicki, T.
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
Published in IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest (2005)
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