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Industrial scale formal verification using concurrent GSTE
by
Jin Yang
,
Ghughal
,
R
.
,
Tiemeyer, A.
Published in
2005 6th International Conference on ASIC
(2005)
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Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU
by
KiranKumar, V. M. Achutha
,
Gupta, A.
,
Ghughal
,
R
.
Published in
2012 Formal Methods in Computer-Aided Design (FMCAD)
(01.10.2012)
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engineering
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formal verification
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circuit simulation
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computer bugs
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concurrent computing
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IEEE/IET Electronic Library (IEL)
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