PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond
Ni, C.-N, Huang, Y.-C, Jun, S., Sun, S., Vyas, A., Khaja, F., Rao, K. V., Sharma, S., Breil, N., Jin, M., Lazik, C., Mayur, A., Gelatos, J., Chung, H., Hung, R., Chudzik, M., Yoshida, N., Kim, N.
Published in 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2016)
Published in 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2016)
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Conference Proceeding
Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
Veloso, A., Demuynck, S., Ercken, M., Goethals, A.M., Locorotondo, S., Lazzarino, F., Altamirano, E., Huffman, C., De Keersgieter, A., Brus, S., Demand, M., Struyf, H., De Backer, J., Hermans, J., Delvaux, C., Baudemprez, B., Vandeweyer, T., Van Roey, F., Baerts, C., Goossens, D., Dekkers, H., Ong, P., Heylen, N., Kellens, K., Volders, H., Hikavyy, A., Vrancken, C., Rakowski, M., Verhaegen, S., Dusa, M., Romijn, L., Pigneret, C., Van Dijk, A., Schreutelkamp, R., Cockburn, A., Gravey, V., Meiling, H., Hultermans, B., Lok, S., Shah, K., Rajagopalan, R., Gelatos, J., Richard, O., Bender, H., Vandenberghe, G., Beyer, G.P., Absil, P., Hoffmann, T., Ronse, K., Biesemans, S.
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
Published in 2009 IEEE International Electron Devices Meeting (IEDM) (01.12.2009)
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(Invited) Conformal Metal Gate Process Technology for 14nm Logic Node and Below
Noori, Atif M, Brand, Adam, Lei, Yu, Chen, Michael, Tang, Wei, Lu, Xinliang, Fu, Xinyu, Ganguli, Seshadri, Anthis, Jeffrey, Thompson, David, Yoshida, Naomi, Xu, Min, Allen, Miller, Yang, Haichun, Gelatos, Jerry, Yu, San-Ho, Chang, Mei, Gandikota, Srinivas
Published in ECS transactions (15.03.2013)
Published in ECS transactions (15.03.2013)
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Journal Article
Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances
NOORI, Atif M, BALSEANU, Mihaela, LAUWERS, Anne, LEE, Wen-Chin, JIANXIN LEI, MANDREKAR, Tushar, SCHREUTELKAMP, Robert, SHAH, Kavita, THOMPSON, Scott E, VERHEYEN, Peter, WANG, Ching-Ya, XIA, Li-Qun, BOELEN, Pieter, ARGHAVANI, Reza, COCKBUM, Andrew, DEMUYNCK, Steven, FELCH, Susan, GANDIKOTA, Srinivas, JERRY GELATOS, A, KHANDELWAL, Amit, KITTL, Jorge A
Published in IEEE transactions on electron devices (01.05.2008)
Published in IEEE transactions on electron devices (01.05.2008)
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Journal Article
Damage engineered Se implant for NMOS TiSix contact resistivity reduction
Rao, K. V., Khaja, F. A., Ni, C. N., Sharma, S., Zheng, B., Ramalingam, J., Gelatos, J., Lei, J., Mayur, A., Hung, R., Banthia, V., Brand, A., Variam, N.
Published in 2014 20th International Conference on Ion Implantation Technology (IIT) (01.06.2014)
Published in 2014 20th International Conference on Ion Implantation Technology (IIT) (01.06.2014)
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Conference Proceeding
Selenium segregation optimization for 10 nm node contact resistivity
Ni, C-N, Rao, K. V., Khaja, F., Sharma, S., Zheng, B., Ramalingam, J., Gelatos, J., Lei, J., Chang, C-P, Mayur, A., Variam, N., Hung, R., Brand, A.
Published in Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2014)
Published in Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2014)
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Conference Proceeding
Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks
Nainani, A., Gupta, S., Moroz, V., Munkang Choi, Yihwan Kim, Cho, Y., Gelatos, J., Mandekar, T., Brand, A., Er-Xuan Ping, Abraham, M. C., Schuegraf, K.
Published in 2012 International Electron Devices Meeting (01.12.2012)
Published in 2012 International Electron Devices Meeting (01.12.2012)
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Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond
Ni, C.-N, Rao, K. V., Khaja, F., Sharma, S., Zheng, B., Ramalingam, J., Gelatos, J., Lei, J., Muthukrishnan, S., Hung, R., Chang, C.-P, Variam, N., Brand, A.
Published in 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2013)
Published in 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) (01.04.2013)
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Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines
Van Olmen, J., List, S., Tokei, Z., Carbonell, L., Brongersma, S.H., Volders, H., Kunnen, E., Heylen, N., Ciofi, I., Khandelwal, A., Gelatos, J., Mandrekar, T., Boelen, P.
Published in 2007 IEEE International Interconnect Technology Conferencee (01.06.2007)
Published in 2007 IEEE International Interconnect Technology Conferencee (01.06.2007)
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Conference Proceeding
Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
Veloso, A., Demuynck, S., Ercken, M., Goethals, A.M., Demand, M., de Marneffe, J.-F., Altamirano, E., De Keersgieter, A., Delvaux, C., De Backer, J., Brus, S., Hermans, J., Baudemprez, B., Van Roey, F., Lorusso, G.F., Baerts, C., Goossens, D., Vrancken, C., Mertens, S., Versluijs, J.J., Truffert, V., Huffman, C., Laidler, D., Heylen, N., Ong, P., Parvais, B., Rakowski, M., Verhaegen, S., Hikavyy, A., Meiling, H., Hultermans, B., Romijn, L., Pigneret, C., Lok, S., Van Dijk, A., Shah, K., Noori, A., Gelatos, J., Arghavani, R., Schreutelkamp, R., Boelen, P., Richard, O., Bender, H., Witters, L., Collaert, N., Rooyackers, R., Absil, P., Lauwers, A., Jurczak, M., Hoffmann, T., Vanhaelemeersch, S., Cartuyvels, R., Ronse, K., Biesemans, S.
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
Published in 2008 IEEE International Electron Devices Meeting (01.12.2008)
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A low temperature CVD Al plug and interconnect process for 0.25 /spl mu/m metallization technologies
Fiordalice, R., Blumenthal, R., Fernandes, M., Garcia, S., Gelatos, J., Kawasaki, H., Klein, J., Marsh, R., Ong, T., Venkatraman, R., Weitzman, E., Pintchovski, F.
Published in 1996 Symposium on VLSI Technology. Digest of Technical Papers (1996)
Published in 1996 Symposium on VLSI Technology. Digest of Technical Papers (1996)
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