A 35.6 TOPS/W/mm² 3-Stage Pipelined Computational SRAM With Adjustable Form Factor for Highly Data-Centric Applications
Noel, J.-P., Pezzin, M., Gauchi, R., Christmann, J.-F., Kooli, M., Charles, H.-P., Ciampolini, L., Diallo, M., Lepin, F., Blampey, B., Vivet, P., Mitra, S., Giraud, B.
Published in IEEE journal of solid-state circuits (2020)
Published in IEEE journal of solid-state circuits (2020)
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Journal Article
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing
Noel, J.-P., Egloff, V., Kooli, M., Gauchi, R., Portal, J.-M., Charles, H.-P., Vivet, P., Giraud, B.
Published in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2020)
Published in 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2020)
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Conference Proceeding
A 35.6TOPS/W/mm$^2$ 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
Noel, J.-P, Pezzin, M., Gauchi, R., Christmann, J.-F, Kooli, M., Charles, Henri-Pierre, Ciampolini, L., Diallo, M., Lepin, F., Blampey, B., Vivet, P., Mitra, S., Giraud, B.
Published in IEEE solid-state circuits letters (22.07.2020)
Published in IEEE solid-state circuits letters (22.07.2020)
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Journal Article