A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter
Amirkhany, A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Kollipara, R.T., Stojanovic, V., Horowitz, M.
Published in IEEE journal of solid-state circuits (01.04.2008)
Published in IEEE journal of solid-state circuits (01.04.2008)
Get full text
Journal Article
Conference Proceeding
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
Stojanovic, V., Ho, A., Garlepp, B.W., Chen, F., Wei, J., Tsang, G., Alon, E., Kollipara, R.T., Werner, C.W., Zerbe, J.L., Horowitz, M.A.
Published in IEEE journal of solid-state circuits (01.04.2005)
Published in IEEE journal of solid-state circuits (01.04.2005)
Get full text
Journal Article
Conference Proceeding
A portable digital DLL for high-speed CMOS interface circuits
Garlepp, B.W., Donnelly, K.S., Jun Kim, Chau, P.S., Zerbe, J.L., Huang, C., Tran, C.V., Portmann, C.L., Stark, D., Yiu-Fai Chan, Lee, T.H., Horowitz, M.A.
Published in IEEE journal of solid-state circuits (01.05.1999)
Published in IEEE journal of solid-state circuits (01.05.1999)
Get full text
Journal Article
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus
Zerbe, J.L., Chau, P.S., Werner, C.W., Thrush, T.P., Liaw, H.J., Garlepp, B.W., Donnelly, K.S.
Published in IEEE journal of solid-state circuits (01.05.2001)
Published in IEEE journal of solid-state circuits (01.05.2001)
Get full text
Journal Article
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system
Werner, C., Hoyer, C., Ho, A., Jeeradit, M., Chen, F., Garlepp, B., Stonecypher, W., Li, S., Akash Bansal, Agarwal, A., Alon, E., Stojanovic, V., Zerbe, J.
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
Published in Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 (2005)
Get full text
Conference Proceeding
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications
Savoj, J., Abbasfar, A., Amirkhany, A., Jeeradit, M., Garlepp, B.W.
Published in IEEE journal of solid-state circuits (01.05.2008)
Published in IEEE journal of solid-state circuits (01.05.2008)
Get full text
Journal Article
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator
Perrott, M H, Pamarti, S, Hoffman, E G, Lee, F S, Mukherjee, S, Lee, C, Tsinker, V, Perumal, S, Soto, B T, Arumugam, N, Garlepp, B W
Published in IEEE journal of solid-state circuits (01.12.2010)
Published in IEEE journal of solid-state circuits (01.12.2010)
Get full text
Journal Article
Conference Proceeding
Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver
Stojanovic, V., Ho, A., Garlepp, B., Chen, F., Wei, J., Alon, E., Werner, C., Zerbe, J., Horowitz, M.A.
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
Published in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) (2004)
Get full text
Conference Proceeding
A 2.5-Gb/s Multi-Rate 0.25-[Formula Omitted]m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition
Perrott, M.H, Huang, Yunteng, Baird, R.T, Garlepp, B.W, Pastorello, D, King, E.T, Yu, Qicheng, Kasha, D.B, Steiner, P, Zhang, Ligang, Hein, J, Del Signore, B
Published in IEEE journal of solid-state circuits (01.12.2006)
Published in IEEE journal of solid-state circuits (01.12.2006)
Get full text
Journal Article
Characterizing sampling aperture of clocked comparators
Jeeradit, M., Kim, J., Leibowitz, B., Nikaeen, P., Wang, V., Garlepp, B., Werner, C.
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Published in 2008 IEEE Symposium on VLSI Circuits (01.06.2008)
Get full text
Conference Proceeding
A 24Gb/s Software Programmable Multi-Channel Transmitter
Amirkhany, A., Abbasfar, A., Savoj, J., Jeeradit, M., Garlepp, B., Stojanovic, V., Horowitz, M.
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
Get full text
Conference Proceeding
A programmable MEMS-based clock generator with sub-ps jitter performance
Lee, F. S., Salvia, J., Lee, C., Mukherjee, S., Melamud, R., Arumugam, N., Pamarti, S., Arft, C., Gupta, P., Tabatabaei, S., Garlepp, B., Hae-Chang Lee, Partridge, A., Perrott, M. H., Assaderaghi, F.
Published in 2011 Symposium on VLSI Circuits - Digest of Technical Papers (01.06.2011)
Get full text
Published in 2011 Symposium on VLSI Circuits - Digest of Technical Papers (01.06.2011)
Conference Proceeding
A 1-10 Gbps PAM2, PAM4, PAM2 partial response receiver analog front end with dynamic sampler swapping capability for backplane serial communications
Garlepp, B., Ho, A., Stojanovic, V., Chen, F., Werner, C., Tsang, G., Thrush, T., Agarwal, A., Zerbe, J.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Get full text
Conference Proceeding
A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs
Portmann, C., Chu, A., Hays, N., Sidiropoulos, S., Stark, D., Chau, P., Donnelly, K., Garlepp, B.
Published in 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) (1999)
Published in 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) (1999)
Get full text
Conference Proceeding