A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS
Gangasani, Gautam R., Kinget, Peter R.
Published in IEEE transactions on circuits and systems. II, Express briefs (01.05.2019)
Published in IEEE transactions on circuits and systems. II, Express briefs (01.05.2019)
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Journal Article
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology
Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.
Published in IEEE journal of solid-state circuits (01.08.2012)
Published in IEEE journal of solid-state circuits (01.08.2012)
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Journal Article
Conference Proceeding
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
Gangasani, Gautam R., Chun-Ming Hsu, Bulzacchelli, John F., Beukema, Troy, Kelly, William, Xu, Hui H., Freitas, David, Prati, Andrea, Gardellini, Daniele, Reutemann, Robert, Cervelli, Giovanni, Hertle, Juergen, Baecher, Matthew, Garlett, Jon, Francese, Pier-Andrea, Ewen, John F., Hanson, David, Storaska, Daniel W., Meghelli, Mounir
Published in IEEE journal of solid-state circuits (01.11.2014)
Published in IEEE journal of solid-state circuits (01.11.2014)
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Journal Article
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
Published in 2011 IEEE Custom Integrated Circuits Conference (CICC) (01.09.2011)
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Conference Proceeding
A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology
Gangasani, Gautam R., Bulzacchelli, John F., Beukema, Troy, Chun-Ming Hsu, Kelly, William, Xu, Hui H., Freitas, David, Prati, Andrea, Gardellini, Daniele, Cervelli, Giovanni, Hertle, Juergen, Baecher, Matthew, Garlett, Jon, Reutemann, Robert, Hanson, David, Storaska, Daniel W., Meghelli, Mounir
Published in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2013)
Published in 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) (01.11.2013)
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Conference Proceeding