A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
Barth, J., Reohr, W.R., Parries, P., Fredeman, G., Golz, J., Schuster, S.E., Matick, R.E., Hunter, H., Tanner, C.C., Harig, J., Kim Hoki, Khan, B.A., Griesemer, J., Havreluk, R.P., Yanagisawa, K., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.01.2008)
Published in IEEE journal of solid-state circuits (01.01.2008)
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Conference Proceeding
Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Batra, Pooja, LaTulipe, Douglas, Skordas, Spyridon, Winstel, Kevin, Kothandaraman, Chandrasekharan, Himmel, Ben, Maier, Gary, He, Bishan, Gamage, Deepal Wehella, Golz, John, Wei Lin, Tuan Vo, Priyadarshini, Deepika, Hubbard, Alex, Cauffman, Kristian, Peethala, Brown, Barth, John, Kirihata, Toshiaki, Graves-Abe, Troy, Robson, Norman, Iyer, Subramanian
Published in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2013)
Published in 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (01.10.2013)
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Conference Proceeding
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
Klim, P.J., Barth, J., Reohr, W.R., Dick, D., Fredeman, G., Koch, G., Le, H.M., Khargonekar, A., Wilcox, P., Golz, J., Kuang, J.B., Mathews, A., Law, J.C., Luong, T., Ngo, H.C., Freese, R., Hunter, H.C., Nelson, E., Parries, P., Kirihata, T., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.04.2009)
Published in IEEE journal of solid-state circuits (01.04.2009)
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Conference Proceeding
An 800-MHz embedded DRAM with a concurrent refresh mode
Kirihata, T., Parries, P., Hanson, D.R., Hoki Kim, Golz, J., Fredeman, G., Rajeevakumar, R., Griesemer, J., Robson, N., Cestero, A., Khan, B.A., Geng Wang, Wordeman, M., Iyer, S.S.
Published in IEEE journal of solid-state circuits (01.06.2005)
Published in IEEE journal of solid-state circuits (01.06.2005)
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Journal Article
FACILITATOR DIES FOR HETEROGENEOUS DIE STACKS
Kim, Kyu-hyoun, Golz, John W, Rubin, Joshua M, Kumar, Arvind, Meghelli, Mounir
Year of Publication 25.07.2024
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Year of Publication 25.07.2024
Patent
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier
Barth, John, Reohr, William, Parries, Paul, Fredeman, Greg, Golz, John, Schuster, Stanley, Matick, Richard, Hunter, Hillery, Tanner, Charles, Harig, Joseph, Kim, Hoki, Khan, Babar, Griesemer, John, Havreluk, Robert, Yanagisawa, Kenji, Kirihata, Toshiaki, Iyer, Subramanian
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
Published in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (01.02.2007)
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Conference Proceeding
ACTIVE BRIDGE FOR CHIPLET AND MODULE INTER-COMMUNICATION
Divakaruni, Ramachandra, Golz, John W, HAN, JIN PING, Kumar, Arvind, Farooq, Mukta Ghate, Meghelli, Mounir
Year of Publication 28.03.2024
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Year of Publication 28.03.2024
Patent
POWER DISTRIBUTION NETWORKS FOR SEMICONDUCTOR CHIP
Clevenger, Lawrence A, Anderson, Brent A, Chu, Albert M, Wang, Junli, Golz, John W, Lanzillo, Nicholas Anthony
Year of Publication 12.10.2023
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Year of Publication 12.10.2023
Patent
relic S-RNase is expressed in the styles of self-compatible Nicotiana sylvestris
Golz, J.F, Clarke, A.E, Newbigin, E, Anderson, M
Published in The Plant journal : for cell and molecular biology (01.12.1998)
Published in The Plant journal : for cell and molecular biology (01.12.1998)
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80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
Viraraghavan, Janakiraman, Leu, Derek, Jayaraman, Balaji, Cestero, Alberto, Kilker, Robert, Ming Yin, Golz, John, Tummuru, Rajesh R., Raghavan, Ramesh, Moy, Dan, Kempanna, Thejas, Khan, Faraz, Kirihata, Toshiaki, Iyer, Subramanian
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (01.06.2016)
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Conference Proceeding
Cloning and Nucleotide Sequence of the $\text{S}_{7}$-RNase from Nicotiana alata Link and Otto
Adrienne Vissers, Peter Dodds, Golz, John F., Clarke, Adrienne E.
Published in Plant physiology (Bethesda) (01.05.1995)
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Published in Plant physiology (Bethesda) (01.05.1995)
Journal Article
An 800MHz embedded DRAM with a concurrent refresh mode
Kirihata, T., Parries, P., Hanson, D., Kim, H., Golz, J., Fredeman, G., Rajeevakumar, R., Griesemer, J., Robson, N., Cestero, A., Wordeman, M., Iyer, S.
Published in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) (2004)
Published in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) (2004)
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Conference Proceeding
Combination of TSV and back side wiring in 3D integration
Winstel Kevin R, Iyer Subramanian S, La Tulipe, Jr. Douglas C, Golz John W, Skordas Spyridon, Batra Pooja R
Year of Publication 10.01.2017
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Year of Publication 10.01.2017
Patent