Reliability Issues in Analog ReRAM Based Neural-Network Processor
Yasuhara, Ryutaro, Ono, Takashi, Mochida, Reiji, Muraoka, Shunsaku, Kouno, Kazuyuki, Katayama, Koji, Hayata, Yuriko, Nakayama, Masayoshi, Suwa, Hitoshi, Hayakawa, Yukio, Mikawa, Takumi, Gohou, Yasushi, Yoneda, Shinichi
Published in 2019 IEEE International Reliability Physics Symposium (IRPS) (01.03.2019)
Published in 2019 IEEE International Reliability Physics Symposium (IRPS) (01.03.2019)
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Conference Proceeding
A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture
Mochida, Reiji, Kouno, Kazuyuki, Hayata, Yuriko, Nakayama, Masayoshi, Ono, Takashi, Suwa, Hitoshi, Yasuhara, Ryutaro, Katayama, Koji, Mikawa, Takumi, Gohou, Yasushi
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Conference Proceeding
Neuromorphic computing based on Analog ReRAM as low power solution for edge application
Mikawa, Takumi, Yasuhara, Ryutaro, Katayama, Koji, Kouno, Kazuyuki, Ono, Takashi, Mochida, Reiji, Hayata, Yuriko, Nakayama, Masayoshi, Suwa, Hitoshi, Gohou, Yasushi, Kakiage, Toru
Published in 2019 IEEE 11th International Memory Workshop (IMW) (01.05.2019)
Published in 2019 IEEE 11th International Memory Workshop (IMW) (01.05.2019)
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Conference Proceeding
A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure
Yamaoka, K., Iwanari, S., Murakuki, Y., Hirano, H., Sakagami, M., Nakakuma, T., Miki, T., Gohou, Y.
Published in IEEE journal of solid-state circuits (01.01.2005)
Published in IEEE journal of solid-state circuits (01.01.2005)
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Journal Article
Conference Proceeding
MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, AND NONVOLATILE STORAGE SYSTEM
IWANARI, SHUNICHI, NAKANISHI, MASAHIRO, TOKUMITSU, SHINICHI, TOYAMA, MASAYUKI, TAMURA, KAZUAKI, GOHOU, YASUSHI, KASAHARA, TETSUSHI, NAKAMURA, YUTAKA, MATSUURA, MASANORI, IZUMI, TOMOAKI, INOUE, MANABU, MATSUNO, KIMINORI
Year of Publication 20.09.2007
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Year of Publication 20.09.2007
Patent
Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure : Materials-related manufacturing issues in the nanochip era
NAGANO, Yoshihisa, MIKAWA, Takumi, GOHOU, Yasushi, JUDAI, Yuji, FUJII, Eiji, KUTSUNAI, Toshie, NATSUME, Shinya, TATSUNARI, Toshitaka, ITO, Toyoji, NOMA, Atsushi, NASU, Toru, HAYASHI, Shinichiro, HIRANO, Hiroshige
Published in IEEE transactions on semiconductor manufacturing (2005)
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Published in IEEE transactions on semiconductor manufacturing (2005)
Journal Article
Embedded ferroelectric memory technology with completely encapsulated hydrogen barrier structure
Nagano, Y., Mikawa, T., Kutsunai, T., Natsume, S., Tatsunari, T., Ito, T., Noma, A., Nasu, T., Hayashi, S., Hirano, H., Gohou, Y., Judai, Y., Fujii, E.
Published in IEEE transactions on semiconductor manufacturing (01.02.2005)
Published in IEEE transactions on semiconductor manufacturing (01.02.2005)
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Journal Article
A 0.9V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure
YAMAOKA, Kunisato, IWANARI, Shunichi, MURAKUKI, Yasuo, HIRANO, Hiroshige, SAKAGAMI, Masahiko, NAKAKUMA, Tetsuji, MIKI, Takashi, GOHOU, Yasushi
Year of Publication 2004
Year of Publication 2004
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Conference Proceeding
Semiconductor memory device and semiconductor memory system
MURAKUKI YASUO, IWANARI SHUNICHI, MATSUURA MASANORI, GOHOU YASUSHI, NAKAO YOSHIAKI
Year of Publication 16.11.2010
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Year of Publication 16.11.2010
Patent
Semiconductor memory device and semiconductor memory system
Murakuki, Yasuo, Gohou, Yasushi, Iwanari, Shunichi, Matsuura, Masanori, Nakao, Yoshiaki
Year of Publication 16.11.2010
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Year of Publication 16.11.2010
Patent
ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM
MURAKUKI YASUO, IWANARI SHUNICHI, MATSUURA MASANORI, GOHOU YASUSHI, NAKAO YOSHIAKI
Year of Publication 28.01.2010
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Year of Publication 28.01.2010
Patent
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM
MURAKUKI YASUO, IWANARI SHUNICHI, MATSUURA MASANORI, GOHOU YASUSHI, NAKAO YOSHIAKI
Year of Publication 01.10.2009
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Year of Publication 01.10.2009
Patent
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
MURAKUKI YASUO, IWANARI SHUNICHI, MATSUURA MASANORI, GOHOU YASUSHI, NAKAO YOSHIAKI
Year of Publication 09.07.2009
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Year of Publication 09.07.2009
Patent