Search Results - "GARVIN; STACY J" :: K.UTB vyhledávací portál

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Method and system for adjusting a frequency range of a delay cell of a VCO

by GARVIN STACY J
Year of Publication 31.05.2005

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Method and system for adjusting a frequency range of a delay cell of a VCO

by Garvin, Stacy J
Year of Publication 31.05.2005

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Method and system for adjusting a frequency range of a delay cell of a VCO

by GARVIN STACY J
Year of Publication 24.02.2005

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Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)

by Cranford, Jr, Hayden C, Garvin, Stacy J, Norman, Vernon R
Year of Publication 26.05.2009

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Transistor switch with integral body connection to prevent latchup

by RASMUS TODD M, GARVIN STACY J, CRANFORD HAYDEN C
Year of Publication 03.02.2009

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Transistor switch with integral body connection to prevent latchup

by Cranford, Hayden C, Garvin, Stacy J, Rasmus, Todd M
Year of Publication 03.02.2009

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Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)

by CRANFORD HAYDEN C.JR, GARVIN STACY J, NORMAN VERNON R
Year of Publication 01.11.2007

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Transistor switch with integral body connection to prevent latchup

by Cranford, Jr, Hayden C, Garvin, Stacy J, Rasmus, Todd M
Year of Publication 11.09.2007

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Patent

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Transistor switch with integral body connection to prevent latchup

by RASMUS TODD M, CRANFORD HAYDEN C.JR, GARVIN STACY J
Year of Publication 03.05.2007

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Patent

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Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)

by CRANFORD, JR. HAYDEN C, GARVIN STACY J, NORMAN VERNON R
Year of Publication 26.05.2009

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Patent

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METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING

by UTTER WAYNE A, CRANFORD HAYDEN C.JR, GARVIN STACY J, RAY SAMUEL T, NORMAN VERNON R
Year of Publication 06.12.2007

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Transistor Switch with Integral Body Connection to Prevent Latchup

by RASMUS TODO M, CRANFORD, JR. HAYDEN C, GARVIN STACY J
Year of Publication 22.11.2007

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Method and system for high frequency clock signal gating

by Cranford, Jr, Hayden C, Garvin, Stacy J, Norman, Vernon R, Ray, Samuel T, Utter, Wayne A
Year of Publication 09.10.2007

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Transistor switch with integral body connection to prevent latchup

by RASMUS TODD M, CRANFORD, JR. HAYDEN C, GARVIN STACY J
Year of Publication 11.09.2007

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Patent

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Method and system for high frequency clock signal gating

by UTTER WAYNE A, CRANFORD HAYDEN C.JR, GARVIN STACY J, RAY SAMUEL T, NORMAN VERNON R
Year of Publication 29.03.2007

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Circuit and method for reducing jitter in a PLL of high speed serial links

by Cranford, Jr, Hayden C, Garvin, Stacy J, Norman, Vernon R, Rasmus, Todd M
Year of Publication 09.05.2006

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Circuit and method for reducing jitter in a PLL of high speed serial links

by RASMUS TODD M, CRANFORD, JR. HAYDEN C, GARVIN STACY J, NORMAN VERNON R
Year of Publication 09.05.2006

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Method and system for high frequency clock signal gating

by CRANFORD, JR. HAYDEN C, UTTER WAYNE A, GARVIN STACY J, RAY SAMUEL T, NORMAN VERNON R
Year of Publication 09.10.2007

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Self-adaptive voltage regulator for a phase-locked loop

by Cranford, Jr, Hayden C, Garvin, Stacy J, Norman, Vernon R, Rasmus, Todd M, Seidel, Peter R
Year of Publication 20.12.2005

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Circuit and method for reducing jitter in a PLL of high speed serial links

by RASMUS TODD M, GARVIN STACY J, NORMAN VERNON R, CRANFORD HAYDEN C
Year of Publication 14.04.2005

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