A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
Zheng, Xuqiang, Wang, Zhijun, Li, Fule, Zhao, Feng, Yue, Shigang, Zhang, Chun, Wang, Zhihua
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2016)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2016)
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Journal Article
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
Zheng, Xuqiang, Zhang, Chun, Lv, Fangxu, Zhao, Feng, Yuan, Shuai, Yue, Shigang, Wang, Ziqiang, Li, Fule, Wang, Zhihua, Jiang, Hanjun
Published in IEEE journal of solid-state circuits (01.11.2017)
Published in IEEE journal of solid-state circuits (01.11.2017)
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Journal Article
A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique
Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2018)
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2018)
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Conference Proceeding
A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication
Peng, Qi, Zhang, Chun, Zhao, Xijin, Sun, Xuguang, Li, Fule, Chen, Hong, Wang, Zhihua
Published in IEEE transactions on industrial electronics (1982) (01.07.2015)
Published in IEEE transactions on industrial electronics (1982) (01.07.2015)
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Journal Article
A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO
Zhang, Lingwei, Jiang, Hanjun, Wei, Jianjun, Dong, Jingjing, Li, Fule, Li, Weitao, Gao, Jia, Cui, Jianwei, Chi, Baoyong, Zhang, Chun, Wang, Zhihua
Published in IEEE journal of solid-state circuits (01.11.2013)
Published in IEEE journal of solid-state circuits (01.11.2013)
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Journal Article
Conference Proceeding
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process
Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
Published in 2018 IEEE International Symposium on Circuits and Systems (ISCAS) (27.05.2018)
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Conference Proceeding
An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC
Li, Weitao, Li, Fule, Yang, Changyi, Li, Shengjing, Wang, Zhihua
Published in China communications (01.05.2015)
Published in China communications (01.05.2015)
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Journal Article
A low-offset dynamic comparator with input offset-cancellation
Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang
Published in 2017 IEEE 12th International Conference on ASIC (ASICON) (01.10.2017)
Published in 2017 IEEE 12th International Conference on ASIC (ASICON) (01.10.2017)
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Conference Proceeding
A calibration technique for SAR ADC based on code density test
Xian Gu, Xiuju He, Fule Li
Published in 2015 IEEE 11th International Conference on ASIC (ASICON) (01.11.2015)
Published in 2015 IEEE 11th International Conference on ASIC (ASICON) (01.11.2015)
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Conference Proceeding
A low-power DC offset calibration method independent of IF gain for zero-IF receiver
Dong, JingJing, Jiang, HanJun, Zhang, LingWei, Wei, JianJun, Li, FuLe, Zhang, Chun, Wang, ZhiHua
Published in Science China. Information sciences (01.10.2014)
Published in Science China. Information sciences (01.10.2014)
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Journal Article
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
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Conference Proceeding
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
Published in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (01.09.2016)
Published in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (01.09.2016)
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Conference Proceeding
Charge-compensation-based reference technique for switched-capacitor ADCs
Ya Wang, Fule Li, Chunying Xue, Zhihua Wang
Published in 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2015)
Published in 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2015)
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Conference Proceeding
A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS
Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
Published in 2017 IEEE Custom Integrated Circuits Conference (CICC) (01.04.2017)
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Conference Proceeding
A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC
Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
Published in 2015 IEEE 11th International Conference on ASIC (ASICON) (01.11.2015)
Published in 2015 IEEE 11th International Conference on ASIC (ASICON) (01.11.2015)
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Conference Proceeding
A 14-bit 200MS/s low-power pipelined flash-SAR ADC
Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
Published in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2015)
Published in 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) (01.08.2015)
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Conference Proceeding