Overcoming the Data Deluge Challenges with Greener Electronics
Lequepeys, J.-R., Duranton, M., Bonnetier, S., Catrou, S., Fournel, R., Ernst, T, Herault, L., Louis, D., Jerraya, A., Valentian, A., Perruchot, F., Signamarcheix, T., Vianello, E., Reita, C.
Published in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (13.09.2021)
Published in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (13.09.2021)
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Conference Proceeding
Overcoming the Data Deluge Challenges with Greener Electronics
Lequepeys, J.-R., Duranton, M., Bonnetier, S., Catrou, S., Fournel, R., Ernst, T, Herault, L., Louis, D., Jerraya, A., Valentian, A., Perruchot, F., Signamarcheix, T., Vianello, E., Reita, C.
Published in ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC) (13.09.2021)
Published in ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC) (13.09.2021)
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Conference Proceeding
Temperature Dependences of the Resistivity and the Ferromagnetic Resonance Linewidth in Permalloy Thin Films
Counil, G., Devolder, T., Kim, J.-V., Crozat, P., Chappert, C., Zoll, S., Fournel, R.
Published in IEEE transactions on magnetics (01.10.2006)
Published in IEEE transactions on magnetics (01.10.2006)
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Journal Article
Conference Proceeding
Lateral and Longitudinal Finite Size Effects in NA-FMR Measurements
Counil, G., Crozat, P., Devolder, T., Chappert, C., Zoll, S., Fournel, R.
Published in IEEE transactions on magnetics (01.10.2006)
Published in IEEE transactions on magnetics (01.10.2006)
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Journal Article
Conference Proceeding
OxRAM for embedded solutions on advanced node: scaling perspectives considering statistical reliability and design constraints
Sandrini, J., Barlas, M., Nodin, J. F., Billoint, O., Molas, G., Fournel, R., Nowak, E., Gaillard, F., Cagli, C., Grenouillet, L., Meli, V., Castellani, N., Hammad, I., Bernasconi, S., Aussenac, F., Van Duijn, S., Audoit, G.
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
Precession-dominated reversal of synthetic antiferromagnets and synthetic ferrimagnets
Maufront, C., Kim, J.-V., Devolder, T., Fournel, R., Chappert, C.
Published in IEEE transactions on magnetics (01.10.2005)
Published in IEEE transactions on magnetics (01.10.2005)
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Journal Article
Conference Proceeding
Optimization of RRAM and OTS selector for advanced low voltage CMOS compatibility
Lopez, J. Minguet, Alfaro Robayo, D., Grenouillet, L., Carabasse, C., Navarro, G., Fournel, R., Sabbione, C., Bernard, M., Billoint, O., Cagli, C., Couture, L., Deleruyelle, D., Bocquet, M., Portal, J. M., Nowak, E., Molas, G.
Published in 2020 IEEE International Memory Workshop (IMW) (01.05.2020)
Published in 2020 IEEE International Memory Workshop (IMW) (01.05.2020)
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Conference Proceeding
A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM
Ranica, R., Villaret, A., Malinge, P., Mazoyer, P., Lenoble, D., Candelier, P., Jacquet, F., Masson, P., Bouchakour, R., Fournel, R., Schoellkopf, J.P., Skotnicki, T.
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
ABCA2 is a strong genetic risk factor for early-onset Alzheimer's disease
Macé, Sandrine, Cousin, Emmanuelle, Ricard, Sylvain, Génin, Emmanuelle, Spanakis, Emmanuel, Lafargue-Soubigou, Carole, Génin, Bérengère, Fournel, Raphaël, Roche, Sandrine, Haussy, Gilles, Massey, Florence, Soubigou, Stéphane, Bréfort, Georges, Benoit, Patrick, Brice, Alexis, Campion, Dominique, Hollis, Melvyn, Pradier, Laurent, Benavides, Jésus, Deleuze, Jean-François
Published in Neurobiology of disease (01.02.2005)
Published in Neurobiology of disease (01.02.2005)
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Journal Article
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit
Andrieu, F., Batude, P., Brunet, L., Fenouillet-Beranger, C., Lattard, D., Thuries, S., Billoint, O., Fournel, R., Vinet, M.
Published in 2018 International Conference on IC Design & Technology (ICICDT) (01.06.2018)
Published in 2018 International Conference on IC Design & Technology (ICICDT) (01.06.2018)
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Conference Proceeding
Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications
Ranica, R., Villaret, A., Malinge, P., Gasiot, G., Mazoyer, P., Roche, P., Candelier, P., Jacquet, F., Masson, P., Bouchakour, R., Fournel, R., Schoellkopf, J.P., Skotnicki, T.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
90nm toggle MRAM array with 0.29/spl mu/m/sup 2/ cells
Durlam, M., Andre, T., Brown, P., Calder, J., Chan, J., Cuppens, R., Dave, R.W., Ditewig, T., DeHerrera, M., Engel, B.N., Feil, B., Frey, C., Galpin, D., Garni, B., Grynkewich, G., Janesky, J., Kerszykowski, G., Lien, M., Martin, J., Nahas, J., Nagel, K., Smith, K., Subramanian, C., Sun, J.J., Tamim, J., Williams, R., Wise, L., Zoll, S., List, F., Fournel, R., Martino, B., Tehrani, S.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)
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Conference Proceeding
Temperature dependence of the high frequency response of Permalloy thin films
Counil, G., Crozat, P., Kim, J., Devolder, T., Chappert, C., Zoll, S., Fournel, R.
Published in INTERMAG 2006 - IEEE International Magnetics Conference (01.05.2006)
Published in INTERMAG 2006 - IEEE International Magnetics Conference (01.05.2006)
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Conference Proceeding
Longitudinal and lateral finite size effects in NA-FMR measurements
Counil, G., Kim, J., Devolder, T., Crozat, P., Chappert, C., Zoll, S., Fournel, R.
Published in INTERMAG 2006 - IEEE International Magnetics Conference (01.05.2006)
Published in INTERMAG 2006 - IEEE International Magnetics Conference (01.05.2006)
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Conference Proceeding
An 8 Mbit DRAM design using a 1 Tbulk cell
Malinge, P., Candelier, P., Jacquet, F., Martin, S., Ranica, R., Villaret, A., Mazoyer, P., Fournel, R., Allard, B.
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
Published in Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005 (2005)
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Conference Proceeding