Search Results - "Flamand, Éric" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

The transprecision computing paradigm: Concept, design, and applications

The transprecision computing paradigm: Concept, design, and applications

by Malossi, A. Cristiano I., Schaffner, Michael, Molnos, Anca, Gammaitoni, Luca, Tagliavini, Giuseppe, Emerson, Andrew, Tomas, Andres, Nikolopoulos, Dimitrios S., Flamand, Eric, Wehn, Norbert
Published in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2018)

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Conference Proceeding

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones

A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones

by Palossi, Daniele, Loquercio, Antonio, Conti, Francesco, Flamand, Eric, Scaramuzza, Davide, Benini, Luca
Published in IEEE internet of things journal (01.10.2019)

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Journal Article

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

by Gautschi, Michael, Schiavone, Pasquale Davide, Traber, Andreas, Loi, Igor, Pullini, Antonio, Rossi, Davide, Flamand, Eric, Gurkaynak, Frank K., Benini, Luca
Published in IEEE transactions on very large scale integration (VLSI) systems (01.10.2017)

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Journal Article

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

by Rossi, Davide, Conti, Francesco, Eggiman, Manuel, Mauro, Alfio Di, Tagliavini, Giuseppe, Mach, Stefan, Guermandi, Marco, Pullini, Antonio, Loi, Igor, Chen, Jie, Flamand, Eric, Benini, Luca
Published in IEEE journal of solid-state circuits (01.01.2022)

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Journal Article

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters

by Chen, Jie, Loi, Igor, Flamand, Eric, Tagliavini, Giuseppe, Benini, Luca, Rossi, Davide
Published in IEEE transactions on very large scale integration (VLSI) systems (01.04.2023)

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Journal Article

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

by Rossi, Davide, Conti, Francesco, Eggiman, Manuel, Mach, Stefan, Mauro, Alfio Di, Guermandi, Marco, Tagliavini, Giuseppe, Pullini, Antonio, Loi, Igor, Chen, Jie, Flamand, Eric, Benini, Luca
Published in 2021 IEEE International Solid- State Circuits Conference (ISSCC) (13.02.2021)

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Conference Proceeding

P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

by Benini, Luca, Flamand, Eric, Fuin, Didier, Melpignano, Diego
Published in Proceedings of the Conference on Design, Automation and Test in Europe (12.03.2012)

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Conference Proceeding

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator

by Benini, L., Flamand, E., Fuin, D., Melpignano, D.
Published in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) (01.03.2012)

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Conference Proceeding

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications

by Melpignano, Diego, Benini, Luca, Flamand, Eric, Jego, Bruno, Lepley, Thierry, Haugou, Germain, Clermidy, Fabien, Dutoit, Denis
Published in DAC Design Automation Conference 2012 (03.06.2012)

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Conference Proceeding

A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

by Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Santos, Cristiano, Beigné, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Dutoit, Denis, Clermidy, Fabien, Chéramy, Séverine, Sheibanyrad, Abbas, Pétrot, Frédéric, Flamand, Eric, Michailos, Jean, Arriordaz, Alexandre, Wang, Lee, Schloeffel, Juergen
Published in IEEE journal of solid-state circuits (01.01.2017)

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Journal Article

A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones

A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones

by Palossi, Daniele, Loquercio, Antonio, Conti, Francesco, Flamand, Eric, Scaramuzza, Davide, Benini, Luca
Published in IEEE internet of things journal (14.05.2019)

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Journal Article

$A 4 \times 4 \times 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links$

A 4 \times 4 \times 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

by Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Santos, Cristiano, Beigne, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Dutoit, Denis, Clermidy, Fabien, Cheramy, S., Sheibanyrad, Abbas, Petrot, Frederic, Flamand, Eric, Michailos, Jean, Arriordaz, Alexandre, Lee Wang, Schloeffel, Juergen
Published in IEEE journal of solid-state circuits (01.01.2017)

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Journal Article

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications

by Davide Schiavone, Pasquale, Conti, Francesco, Rossi, Davide, Gautschi, Michael, Pullini, Antonio, Flamand, Eric, Benini, Luca
Published in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) (01.09.2017)

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Conference Proceeding

PRO3D, Programming for Future 3D Manycore Architectures: Project’s Interim Status

PRO3D, Programming for Future 3D Manycore Architectures: Project’s Interim Status

by Fabre, Christian, Bacivarov, Iuliana, Basu, Ananda, Ruggiero, Martino, Atienza, David, Flamand, Éric, Krimm, Jean-Pierre, Mottin, Julien, Schor, Lars, Kumar, Pratyush, Yang, Hoeseok, Chokshi, Devesh B., Thiele, Lothar, Bensalem, Saddek, Bozga, Marius, Benini, Luca, Sabry, Mohamed M., Leblebici, Yusuf, De Micheli, Giovanni, Melpignano, Diego
Published in Formal Methods for Components and Objects

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Book Chapter

Self-Learning for Personalized Keyword Spotting on Ultra-Low-Power Audio Sensors

Self-Learning for Personalized Keyword Spotting on Ultra-Low-Power Audio Sensors

by Rusci, Manuele, Paci, Francesco, Fariselli, Marco, Flamand, Eric, Tuytelaars, Tinne
Year of Publication 22.08.2024

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Journal Article

Accelerating RNN-based Speech Enhancement on a Multi-Core MCU with Mixed FP16-INT8 Post-Training Quantization

Accelerating RNN-based Speech Enhancement on a Multi-Core MCU with Mixed FP16-INT8 Post-Training Quantization

by Rusci, Manuele, Fariselli, Marco, Croome, Martin, Paci, Francesco, Flamand, Eric
Year of Publication 14.10.2022

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Journal Article

Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs

Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs

by Fariselli, Marco, Rusci, Manuele, Cambonie, Joel, Flamand, Eric
Published in 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) (06.06.2021)

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Conference Proceeding

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters

Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters

by Chen, Jie, Loi, Igor, Flamand, Eric, Tagliavini, Giuseppe, Benini, Luca, Rossi, Davide
Published in arXiv.org (04.09.2023)

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Paper Journal Article

8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links

8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links

by Vivet, Pascal, Thonnart, Yvain, Lemaire, Romain, Beigne, Edith, Bernard, Christian, Darve, Florian, Lattard, Didier, Miro-Panades, Ivan, Santos, Cristiano, Clermidy, Fabien, Cheramy, Severine, Petrot, Frederic, Flamand, Eric, Michailos, Jean
Published in 2016 IEEE International Solid-State Circuits Conference (ISSCC) (01.01.2016)

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Conference Proceeding

Self-Learning for Personalized Keyword Spotting on Ultra-Low-Power Audio Sensors

Self-Learning for Personalized Keyword Spotting on Ultra-Low-Power Audio Sensors

by Rusci, Manuele, Paci, Francesco, Fariselli, Marco, Flamand, Eric, Tuytelaars, Tinne
Published in arXiv.org (22.08.2024)

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Paper