An inter-die variability compensation scheme for 0.42-V 486-kb FD-SOI SRAM using substrate control
Fujiwara, H., Takeuchi, T., Otake, Yu, Yoshimoto, M., Kawaguchi, H.
Published in 2008 IEEE International SOI Conference (01.10.2008)
Published in 2008 IEEE International SOI Conference (01.10.2008)
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Conference Proceeding
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
Osada, Yoshiaki, Nakazato, Takaaki, Aoyagi, Yumito, Nii, Koji, Liaw, Jhon-Jhy, Wu, Shien-Yang, Li, Quincy, Fujiwara, Hidehiro, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
Published in IEEE journal of solid-state circuits (16.08.2024)
Published in IEEE journal of solid-state circuits (16.08.2024)
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Journal Article
Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential
Noguchi, Hiroki, Iguchi, Yusuke, Fujiwara, Hidehiro, Okumura, Shunsuke, Nii, Koji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
Published in IPSJ Transactions on System LSI Design Methodology (2011)
Published in IPSJ Transactions on System LSI Design Methodology (2011)
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Journal Article
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
Yabuuchi, Makoto, Tsukamoto, Yasumasa, Fujiwara, Hidehiro, Tanaka, Miki, Shinji, Shinji, Nii, Koji
Published in IEEE transactions on very large scale integration (VLSI) systems (01.11.2018)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.11.2018)
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Journal Article
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low- V MIN Applications
Chang, Tsung-Yung Jonathan, Chen, Yen-Huei, Chan, Wei-Min, Cheng, Hank, Wang, Po-Sheng, Lin, Yangsyu, Fujiwara, Hidehiro, Lee, Robin, Liao, Hung-Jen, Wang, Ping-Wei, Yeap, Geoffrey, Li, Quincy
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros
Sun, Xiaoyu, Cao, Weidong, Crafton, Brian, Akarvardar, Kerem, Mori, Haruki, Fujiwara, Hidehiro, Noguchi, Hiroki, Chih, Yu-Der, Chang, Meng-Fan, Wang, Yih, Chang, Tsung-Yung Jonathan
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.04.2024)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.04.2024)
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Journal Article
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications
Chang, Tsung-Yung Jonathan, Chen, Yen-Huei, Chan, Wei-Min, Cheng, Hank, Wang, Po-Sheng, Lin, Yangsyu, Fujiwara, Hidehiro, Lee, Robin, Liao, Hung-Jen, Wang, Ping-Wei, Yeap, Geoffrey, Li, Quincy
Published in IEEE journal of solid-state circuits (01.01.2021)
Published in IEEE journal of solid-state circuits (01.01.2021)
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Journal Article
An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment
Morita, Y., Fujiwara, H., Noguchi, H., Iguchi, Y., Nii, K., Kawaguchi, H., Yoshimoto, M.
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
Published in 2007 IEEE Symposium on VLSI Circuits (01.06.2007)
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Conference Proceeding
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications
Lee, Chia-Fu, Lu, Cheng-Han, Lee, Cheng-En, Mori, Haruki, Fujiwara, Hidehiro, Shih, Yi-Chun, Chou, Tan-Li, Chih, Yu-Der, Chang, Tsung-Yung Jonathan
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
Published in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (12.06.2022)
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Conference Proceeding