Method to test the resistance of an integrated circuit to a side channel attack
GAGNEROT, GEORGES, FEIX, BENOIT, VERNEUIL, VINCENT, ROUSSELLET, MYLENE
Year of Publication 14.09.2011
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Year of Publication 14.09.2011
Patent
Method for testing resistor of integrated circuit arranged in smart card, involves performing statistical processing step for subset of lateral points using estimated value of physical parameters if general hypothesis is correct
ROUSSELLET MYLENE, VERNEUIL VINCENT, FEIX BENOIT JEAN, GAGNEROT GEORGES ANDRE
Year of Publication 02.09.2011
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Year of Publication 02.09.2011
Patent
Integrated circuit for e.g. smart card, has multiplier executing successive multiplications of binary words by modifying order in which elementary steps of multiplication of components of words are executed, in pseudo-random/random manner
ROUSSELLET MYLENE, VERNEUIL VINCENT, FEIX BENOIT JEAN, GAGNEROT GEORGES ANDRE
Year of Publication 02.09.2011
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Year of Publication 02.09.2011
Patent
METHOD FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO AN ANALYSIS BY AUXILIARY CHANNEL
GAGNEROT, GEORGES, FEIX, BENOIT, VERNEUIL, VINCENT, ROUSSELLET, MYLENE
Year of Publication 01.09.2011
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Year of Publication 01.09.2011
Patent
INTEGRATED CIRCUIT PROTECTED AGAINST A HORIZONTAL AUXILIARY CHANNEL ANALYSIS
GAGNEROT, GEORGES, FEIX, BENOIT, VERNEUIL, VINCENT, ROUSSELLET, MYLENE
Year of Publication 01.09.2011
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Year of Publication 01.09.2011
Patent
Method to test the resistance of an integrated circuit to a side channel attack
Gagnerot, Georges, Roussellet, Mylène, Feix, Benoît, Verneuil, Vincent
Year of Publication 12.04.2017
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Year of Publication 12.04.2017
Patent