Novel High-Performance Analog Devices for Advanced Low-Power High-$k$ Metal Gate Complementary Metal--Oxide--Semiconductor Technology
Han, Jin-Ping, Shimizu, Takashi, Pan, Li-Hong, Voelker, Moritz, Bernicot, Christophe, Arnaud, Franck, Mocuta, Anda, Stahrenberg, Knut, Azuma, Atsushi, Eller, Manfred, Yang, Guoyong, Jaeger, Daniel, Zhuang, Haoren, Miyashita, Katsura, Stein, Kenneth, Nair, Deleep, Park, Jae Hoo, Kohler, Sabrina, Hamaguchi, Masafumi, Li, Weipeng, Kim, Kisang, Chanemougame, Daniel, Kim, Nam Sung, Uchimura, Sadaharu, Tsutsui, Gen, Wiedholz, Christian, Miyake, Shinich, Meer, Hans van, Liang, Jewel, Ostermayr, Martin, Lian, Jenny, Celik, Muhsin, Donaton, Ricardo, Barla, Kathy, Na, MyungHee, Goto, Yoshiro, Sherony, Melanie, Johnson, Frank S, Wachnik, Richard, Sudijono, John, Kaste, Ed, Sampson, Ron, Ku, Ja-Hum, Steegen, An, Neumueller, Walter
Published in Japanese Journal of Applied Physics (01.04.2011)
Published in Japanese Journal of Applied Physics (01.04.2011)
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Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance
King, M. P., Wu, X., Eller, Manfred, Samavedam, Srikanth, Shaneyfelt, M. R., Silva, A. I., Draper, B. L., Rice, W. C., Meisenheimer, T. L., Felix, J. A., Shetler, K. J., Zhang, E. X., Haeffner, T. D., Ball, D. R., Alles, M. L., Kauppila, J. S., Massengill, L. W.
Published in IEEE transactions on nuclear science (07.12.2016)
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Published in IEEE transactions on nuclear science (07.12.2016)
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Influence of stress induced CT local layout effect (LLE) on 14nm FinFET
Pei Zhao, Pandey, Shesh Mani, Banghart, Edmund, Xiaoli He, Asra, Ram, Mahajan, Vinayak, Haojun Zhang, Baofu Zhu, Yamada, Kenta, Linjun Cao, Balasubramaniam, Pala, Joshi, Manoj, Eller, Manfred, Benistant, Francis, Samavedam, Srikanth
Published in 2017 Symposium on VLSI Technology (01.06.2017)
Published in 2017 Symposium on VLSI Technology (01.06.2017)
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Conference Proceeding
Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond
Singh, Jagar, Jerome, Ciavatti, Wei, Andy, Miller, Roderick, Arnaud, Bousquet, Lili, Cheng, Hui Zang, Kasun, Punchihewa, Manjunatha, Prabhu, Biswanath, Senapati, Kumar, Anil, Pandey, Shesh Mani, Iyer, Natarajan M., Mittal, Anurag, Carter, Rick, Lun Zhao, Manfred, Eller, Samavedam, Srikanth
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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Conference Proceeding
Blanket SMT With In Situ N2 Plasma Treatment on the (100) Wafer for the Low-Cost Low-Power Technology Application
JUN YUAN, CHAN, Victor, BELYANSKY, Michael P, ELLER, Manfred, YONG MENG LEE, CAVE, Nigel, HUILING SHANG, YING LI, DIVAKARUNI, Rama, ROVEDO, Nivo, SARDESAI, Viraj, KANIKE, Narasimhulu, VARADARAJAN, Vidya, YU, Mickey, JONG HO YANG, JEONG, Y. K, SUNG KWON, O
Published in IEEE electron device letters (01.09.2009)
Published in IEEE electron device letters (01.09.2009)
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METHOD FOR GENERATING AN EMBEDDED RESISTOR IN A SEMICONDUCTOR DEVICE
RYOU, CHOONG RYUL, KIM, NAM SUNG, SAMAVEDAM SRIKANTH BALAJI, YUAN JUN, KANIKE NARASIMHULU, LEE, SEUNG HWAN, ELLER MANFRED, CHAN VICTOR
Year of Publication 12.08.2010
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Year of Publication 12.08.2010
Patent
Novel High-Performance Analog Devices for Advanced Low-Power High- k Metal Gate Complementary Metal–Oxide–Semiconductor Technology
Han, Jin-Ping, Shimizu, Takashi, Pan, Li-Hong, Voelker, Moritz, Bernicot, Christophe, Arnaud, Franck, Mocuta, Anda, Stahrenberg, Knut, Azuma, Atsushi, Eller, Manfred, Yang, Guoyong, Jaeger, Daniel, Zhuang, Haoren, Miyashita, Katsura, Stein, Kenneth, Nair, Deleep, Park, Jae Hoo, Kohler, Sabrina, Hamaguchi, Masafumi, Li, Weipeng, Kim, Kisang, Chanemougame, Daniel, Kim, Nam Sung, Uchimura, Sadaharu, Tsutsui, Gen, Wiedholz, Christian, Miyake, Shinich, Meer, Hans van, Liang, Jewel, Ostermayr, Martin, Lian, Jenny, Celik, Muhsin, Donaton, Ricardo, Barla, Kathy, Goto, Yoshiro, Sherony, Melanie, Johnson, Frank S., Wachnik, Richard, Sudijono, John, Kaste, Ed, Sampson, Ron, Ku, Ja-Hum, Steegen, An, Neumueller, Walter
Published in Japanese Journal of Applied Physics (01.04.2011)
Published in Japanese Journal of Applied Physics (01.04.2011)
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Journal Article
Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance
Tilke, A.T., Stapelmann, C., Eller, M., Bach, K.-H., Hampp, R., Lindsay, R., Conti, R., Wille, W., Jaiswal, R., Galiano, M., Jain, A.
Published in IEEE transactions on semiconductor manufacturing (01.05.2007)
Published in IEEE transactions on semiconductor manufacturing (01.05.2007)
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Journal Article
Shallow trench isolation for the 45-nm CMOS node and geometry dependence of STI stress on CMOS device performance : The advanced semiconductor manufacturing conference
TILKE, Armin T, STAPELMANN, Chris, JAIN, Alok, ELLER, Manfred, BACH, Karl-Heinz, HAMPP, Roland, LINDSAY, Richard, CONTI, Richard, WILLE, William, JAISWAL, Rakesh, GALIANO, Maria
Published in IEEE transactions on semiconductor manufacturing (2007)
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Published in IEEE transactions on semiconductor manufacturing (2007)
Journal Article