Fogging effect correction method in high-resolution electron beam lithography
Hudek, Peter, Denker, Ulrich, Beyer, Dirk, Belic, Nikola, Eisenmann, Hans
Published in Microelectronic engineering (01.05.2007)
Published in Microelectronic engineering (01.05.2007)
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Journal Article
Conference Proceeding
Generic global placement and floorplanning
Eisenmann, Hans, Johannes, Frank M.
Published in Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) (01.01.1998)
Published in Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) (01.01.1998)
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Conference Proceeding
Direct probing characterization vehicle test chip for wafer level exploration of transistor pattern on product chips
Hess, Christopher, Weiland, Larg, Joag, Amit, Murugan, Balasubramania, Sa Zhao, Doong, Kelvin, Lin, Scott, Eisenmann, Hans
Published in 2014 International Conference on Microelectronic Test Structures (ICMTS) (01.03.2014)
Published in 2014 International Conference on Microelectronic Test Structures (ICMTS) (01.03.2014)
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Conference Proceeding
Direct probing characterization vehicle for transistor, capacitor and resistor testing
Huang, Cho-Si, Doong, Yih-Yuh, Michaels, Kimon, Eisenmann, Hans, Shen, Tzupin, Lin, Chia-Chi, Lin, Sheng-Che, Hess, Christopher
Year of Publication 13.08.2019
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Year of Publication 13.08.2019
Patent
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 31.08.2021
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Year of Publication 31.08.2021
Patent
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 03.08.2021
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Year of Publication 03.08.2021
Patent
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 03.08.2021
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Year of Publication 03.08.2021
Patent
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 27.07.2021
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Year of Publication 27.07.2021
Patent
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 25.05.2021
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Year of Publication 25.05.2021
Patent
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Moe, Matthew, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 13.04.2021
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Year of Publication 13.04.2021
Patent
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 01.12.2020
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Year of Publication 01.12.2020
Patent
IC with test structures embedded within a contiguous standard cell area
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 15.09.2020
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Year of Publication 15.09.2020
Patent
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 17.03.2020
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Year of Publication 17.03.2020
Patent
Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 14.05.2019
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Year of Publication 14.05.2019
Patent
Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 23.04.2019
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Year of Publication 23.04.2019
Patent
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas
Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 19.02.2019
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Year of Publication 19.02.2019
Patent