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Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 19.02.2019

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Patent

Measurement error correction method for correction of errors resulting from the physical properties of a measurement instrument, whereby simulation measurements are compared with actual measurements in an iterative process

Measurement error correction method for correction of errors resulting from the physical properties of a measurement instrument, whereby simulation measurements are compared with actual measurements in an iterative process

by EISENMANN, HANS, PETER, KAI
Year of Publication 26.02.2004

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and corner short test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage

Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas

Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and chamfer short test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective chamfer short, corner short, and via open test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, chamfer short, and via open test areas

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 05.02.2019

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Patent

Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 23.10.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 09.10.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 09.10.2018

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Patent

Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells

Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 29.05.2018

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Patent

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 24.04.2018

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Patent

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Vallishayee, Rakesh, Lee, Sherry, Liao, Marci, Weiland, Larg, Strojwas, Marcin, Ciplickas, Dennis, Michaels, Kimon, Rovner, Vyacheslav, Strojwas, Andrzej, Hess, Christopher, Matsuhashi, Hideki, Lam, Stephen, Fiscus, Timothy, Cheng, Jeremy, Comensoli, Simone, Brozek, Tomasz, Doong, Kelvin, Taylor, Carl, De, Indranil, Haigh, Jonathan, Kibarian, John, Rauscher, Markus, Yokoyama, Nobuharu, O'Sullivan, Conor, Eisenmann, Hans, Lin, Sheng-Che
Year of Publication 17.04.2018

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Patent

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.03.2018

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Patent

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells

by Cheng Jeremy, De Indranil, Eisenmann Hans, Matsuhashi Hideki, Yokoyama Nobuharu, Lin Sheng-Che, Vallishayee Rakesh, Doong Kelvin, Liao Marci, Strojwas Andrzej, Ciplickas Dennis, Brozek Tomasz, Hess Christopher, Fiscus Timothy, Taylor Carl, Weiland Larg, Lee Sherry, Rovner Vyacheslav, Lam Stephen, Haigh Jonathan, O'Sullivan Conor, Michaels Kimon, Comensoli Simone, Strojwas Marcin, Rauscher Markus, Kibarian John
Year of Publication 27.03.2018

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Patent

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