A highly integrated 40-MIPS (peak) 64-b RISC microprocessor
Miyake, J., Maeda, T., Nishimichi, Y., Katsura, J., Taniguchi, T., Yamaguchi, S., Edamatsu, H., Watari, S., Takagi, Y., Tsuji, K., Kuninobu, S., Cox, S., Duschatko, D., MacGregor, D.
Published in IEEE journal of solid-state circuits (01.10.1990)
Published in IEEE journal of solid-state circuits (01.10.1990)
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Journal Article
A 40 MIPS (peak) 64-bit microprocessor with one-clock physical cache load/store
Miyake, J., Maeda, T., Nishimichi, Y., Katsura, J., Tainguchi, T., Yamaguchi, S., Edamatsu, H., Watari, S., Takagi, Y., Tsuji, K., Kuninobu, S., Cox, S., Duschatko, D., MacGregor, D.
Published in 1990 37th IEEE International Conference on Solid-State Circuits (1990)
Published in 1990 37th IEEE International Conference on Solid-State Circuits (1990)
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Conference Proceeding