Modeling Oscillator Injection Locking Using the Phase Domain Response
Dunwell, Dustin, Carusone, Anthony Chan
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2013)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.11.2013)
Get full text
Journal Article
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters
Shuai Chen, Luke Wang, Hong Zhang, Murugesu, Rosanah, Dunwell, Dustin, Carusone, Anthony Chan
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2017)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.09.2017)
Get full text
Journal Article
Computer design of super-orthogonal space-time trellis codes
Bale, M., Laska, B., Dunwell, D., Chan, F., Jafarkhani, H.
Published in IEEE transactions on wireless communications (01.02.2007)
Published in IEEE transactions on wireless communications (01.02.2007)
Get full text
Journal Article
Co-Design of Inter-Chiplet, Package, and System Interconnect Protocols
Carusone, Tony Chan, Dunwell, Dustin, Gupta, Sundeep, Giuliano, Letizia, Auge, Adrien, Klempa, Michael, Fung, Sue Hung
Published in IEEE MICRO (23.08.2024)
Published in IEEE MICRO (23.08.2024)
Get full text
Journal Article
A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS
Dehlaghi, Behzad, Tang, Kerry, Chan Carusone, Anthony, Cassan, David, Tonietto, Davide, Shahramian, Shayan, Liang, Joshua, Bespalko, Ryan, Dunwell, Dustin, Bailey, James, Wang, Bo, Sharif-Bakhtiar, Alireza, O'Farrell, Michael
Published in IEEE solid-state circuits letters (01.11.2019)
Published in IEEE solid-state circuits letters (01.11.2019)
Get full text
Journal Article
30.5 A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS
Shahramian, Shayan, Dehlaghi, Behzad, Liang, Joshua, Bespalko, Ryan, Dunwell, Dustin, Bailey, James, Wang, Bo, Sharif-Bakhtiar, Alireza, O'Farrell, Michael, Tang, Kerry, Carusone, Anthony Chan, Cassan, David, Tonietto, Davide
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Published in 2019 IEEE International Solid- State Circuits Conference - (ISSCC) (01.02.2019)
Get full text
Conference Proceeding
Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation
Zhang, Yi Fan, Liang, Joshua, Shahramian, Shayan, Dehlaghi, Behzad, Bespalko, Ryan, O'Farrel, Michael, Dunwell, Dustin, Tonietto, Davide, Chan Carusone, Anthony
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
Get full text
Journal Article
Channel characterization using jitter measurements
Dunwell, Dustin, Gupta, Atul, Carusone, Anthony Chan
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
Published in 2013 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2013)
Get full text
Conference Proceeding
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver
Dunwell, Dustin, Carusone, Anthony Chan
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
Published in IEEE Custom Integrated Circuits Conference 2010 (01.09.2010)
Get full text
Conference Proceeding
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC
Bichan, Mike, Dunwell, Dustin, Qiwei Wang, Carusone, Anthony Chan
Published in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (01.06.2014)
Published in 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (01.06.2014)
Get full text
Conference Proceeding
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS
Dunwell, D, Carusone, A C
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Published in 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (01.05.2010)
Get full text
Conference Proceeding
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on
Dunwell, D., Carusone, A. C., Zerbe, J., Leibowitz, B., Daly, B., Eble, J.
Published in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference (01.09.2012)
Published in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference (01.09.2012)
Get full text
Conference Proceeding