Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method
Galy, P., Berland, V., Foucher, B., Lombaert-Valot, I., Guilhaume, A., Chante, J.P., Dufrenne, S., Bardy, S.
Published in Microelectronics and reliability (01.08.2000)
Published in Microelectronics and reliability (01.08.2000)
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Journal Article
Investigation of post STI liner oxide annealing effect in 0.14μm embedded flash technology
Li Juan Jin, Young Seon You, Jin Yu, Dufrenne, S., Eng Keong Ho, Shukla, D., Mukhopadhyay, M., Kin San Pey
Published in 2006 IEEE International Symposium on Semiconductor Manufacturing (01.09.2006)
Published in 2006 IEEE International Symposium on Semiconductor Manufacturing (01.09.2006)
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Conference Proceeding