Quantum Circuit Simplification and Level Compaction
Maslov, D., Dueck, G.W., Miller, D.M., Negrevergne, C.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2008)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2008)
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Journal Article
Reversible cascades with minimal garbage
Maslov, D., Dueck, G.W.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2004)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2004)
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Journal Article
Toffoli network synthesis with templates
Maslov, D., Dueck, G.W., Miller, D.M.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.2005)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.06.2005)
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Journal Article
Synthesis of Fredkin-Toffoli reversible networks
Maslov, D., Dueck, G.W., Miller, D.M.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2005)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.06.2005)
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Journal Article
Comments on "Sympathy: fast exact minimization of fixed polarity Reed-Muller expansion for symmetric functions"
Butler, J.T., Dueck, G.W., Shmerko, V.P., Yanuskevich, S.
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2000)
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01.11.2000)
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Journal Article
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Wille, R., Grosse, D., Teuber, L., Dueck, G.W., Drechsler, R.
Published in 38th International Symposium on Multiple Valued Logic (ismvl 2008) (01.05.2008)
Published in 38th International Symposium on Multiple Valued Logic (ismvl 2008) (01.05.2008)
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Conference Proceeding
Reversible Logic Synthesis with Output Permutation
Wille, R., Grosse, D., Dueck, G.W., Drechsler, R.
Published in 2009 22nd International Conference on VLSI Design (01.01.2009)
Published in 2009 22nd International Conference on VLSI Design (01.01.2009)
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Conference Proceeding
Generating Toffoli networks from ESOP expressions
Sanaee, Y., Dueck, G.W.
Published in 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (01.08.2009)
Published in 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (01.08.2009)
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Conference Proceeding
Quantified Synthesis of Reversible Logic
Wille, R., Le, H.M., Dueck, G.W., Grosse, D.
Published in 2008 Design, Automation and Test in Europe (01.03.2008)
Published in 2008 Design, Automation and Test in Europe (01.03.2008)
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Conference Proceeding
Quantum Circuit Simplification Using Templates
Maslov, D., Young, C., Miller, D. M., Dueck, G. W.
Published in Design, Automation and Test in Europe (07.03.2005)
Published in Design, Automation and Test in Europe (07.03.2005)
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Conference Proceeding
Debugging of Toffoli networks
Wille, R., Grosse, D., Frehse, S., Dueck, G.W., Drechsler, R.
Published in 2009 Design, Automation & Test in Europe Conference & Exhibition (01.04.2009)
Published in 2009 Design, Automation & Test in Europe Conference & Exhibition (01.04.2009)
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Conference Proceeding
A synthesis method for MVL reversible logic [multiple value logic]
Miller, D.M., Dueck, G.W., Maslov, D.
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
Published in Proceedings. 34th International Symposium on Multiple-Valued Logic (2004)
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Conference Proceeding
Level Compaction in Quantum Circuits
Maslov, D., Dueck, G.W.
Published in 2006 IEEE International Conference on Evolutionary Computation (2006)
Published in 2006 IEEE International Conference on Evolutionary Computation (2006)
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Conference Proceeding
Templates for reversible circuit simplification
Maslov, D., Miller, D.M., Dueck, G.W.
Published in PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005 (2005)
Published in PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005 (2005)
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Conference Proceeding
On the size of multiple-valued decision diagrams
Miller, D.M., Dueck, G.W.
Published in 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings (2003)
Published in 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings (2003)
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Conference Proceeding
On the number of generators for transeunt triangles
Butler, J.T., Dueck, G.W., Yanushkevich, S.N., Shmerko, V.P.
Published in Discrete Applied Mathematics (15.03.2001)
Published in Discrete Applied Mathematics (15.03.2001)
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Journal Article