High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process
Do, Minh Q., Per Larsson-Edefors, Per, Drazdziulis, Mindaugas
Published in 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (01.08.2007)
Published in 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (01.08.2007)
Get full text
Conference Proceeding
Evaluation of power cut-off techniques in the presence of gate leakage
Drazdziulis, M., Larsson-Edefors, P.
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)
Get full text
Conference Proceeding
Evaluation of power cut-off techniques in the presence of gate leakage
Get full text
Conference Proceeding
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
Do, Minh Q., Drazdziulis, Mindaugas, Larsson-Edefors, Per, Bengtsson, Lars
Published in 7th International Symposium on Quality Electronic Design (ISQED'06) (01.01.2006)
Published in 7th International Symposium on Quality Electronic Design (ISQED'06) (01.01.2006)
Get full text
Conference Proceeding
Overdrive Power-Gating Techniques for Total Power Minimization
Drazdziulis, M., Larsson-Edefors, P., Svensson, L.
Published in IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) (01.03.2007)
Published in IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) (01.03.2007)
Get full text
Conference Proceeding