A 76-mm(2) 8-Mb chain ferroelectric memory
Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2010)
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Journal Article
A 76-mm super(2) 8-Mb chain ferroelectric memory
Takashima, D, Takeuchi, T, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y
Published in IEEE journal of solid-state circuits (01.11.2001)
Published in IEEE journal of solid-state circuits (01.11.2001)
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Journal Article
A 0.5-mu m, 3-V 1T1C, 1-Mbit FRAM with a variable referencebit-line voltage scheme using a fatigue-free reference capacitor
Ogiwara, R, Tanaka, S, Itoh, Y, Miyakawa, T, Takeuchi, Y, Doumae, S M, Takenaka, H, Kunishima, I, Shuto, S, Hidaka, O, Ohtsuki, S
Published in IEEE journal of solid-state circuits (01.04.2000)
Published in IEEE journal of solid-state circuits (01.04.2000)
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Journal Article
0.5- mu m, 3-V, 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor
Ogiwara, Ryu, Tanaka, Sumio, Itoh, Yasuo, Miyakawa, Tadashi, Takeuchi, Yoshiaki, Doumae, Sumiko Mano, Takenaka, Hiroyuki, Kunishima, Iwao, Shuto, Susumu, Hidaka, Osamu, Ohtsuki, Sumito, Tanaka, Shin-ichi
Published in IEEE journal of solid-state circuits (2000)
Published in IEEE journal of solid-state circuits (2000)
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Journal Article