Search Results - "Djaja, Gregory" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

by Narasimham, B., Chandrasekharan, K., Liu, Z., Wang, J. K., Djaja, G., Gaspard, N. J., Kauppila, J. S., Bhuva, B. L.
Published in IEEE transactions on nuclear science (01.12.2012)

Get full text

Journal Article

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process

by Narasimham, Balaji, Chandrasekharan, Karthik, Wang, Jung K., Djaja, Gregory, Gaspard, Nelson J., Mahatme, Nihaar N., Assis, Thiago R., Bhuva, Bharat L.
Published in 2014 IEEE International Reliability Physics Symposium (01.06.2014)

Get full text

Conference Proceeding

Evaluation of logic SER for a network processor and the use of targeted hardening to improve system SER performance

Evaluation of logic SER for a network processor and the use of targeted hardening to improve system SER performance

by Narasimham, B., Risch, S., Wang, J. K., Spillane, J., Keegan, L., Chandrasekharan, K., Djaja, G.
Published in 2013 IEEE International Reliability Physics Symposium (IRPS) (01.04.2013)

Get full text

Conference Proceeding

Data retention flip flop for low power applications

Data retention flip flop for low power applications

by Djaja, Gregory, Chandrasekharan, Karthik
Year of Publication 27.12.2011

Get full text

Patent

Data retention flip flop for low power applications

Data retention flip flop for low power applications

by DJAJA GREGORY, CHANDRASEKHARAN KARTHIK
Year of Publication 27.12.2011

Get full text

Patent

Data retention flip flop for low power applications

Data retention flip flop for low power applications

by DJAJA GREGORY, CHANDRASEKHARAN KARTHIK
Year of Publication 07.01.2010

Get full text

Patent

Hysteresis-based latch design for improved soft error rate with low area/performance overhead

Hysteresis-based latch design for improved soft error rate with low area/performance overhead

by DJAJA GREGORY, CHANDRASEKHARAN KARTHIK, NARASIMHAM BALAJI
Year of Publication 13.05.2014

Get full text

Patent

Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead

Hysteresis-Based Latch Design for Improved Soft Error Rate with Low Area/Performance Overhead

by DJAJA GREGORY, CHANDRASEKHARAN KARTHIK, NARASIMHAM BALAJI
Year of Publication 12.09.2013

Get full text

Patent

Low leakage data retention flip flop

Low leakage data retention flip flop

by DJAJA GREGORY, SLAMOWITZ MARK, CHANDRASEKHARAN KARTHIK
Year of Publication 13.12.2011

Get full text

Patent

Low leakage data retention flip flop

Low leakage data retention flip flop

by Djaja, Gregory, Slamowitz, Mark, Chandrasekharan, Karthik
Year of Publication 13.12.2011

Get full text

Patent

Scalable serializer

Scalable serializer

by GORTI RAMAMURTHY, DJAJA GREGORY, CHEN HUA-FENG, CHANDRASEKHARAN KARTHIK, SMITH DOUGLAS
Year of Publication 22.09.2015

Get full text

Patent

Low leakage data retention flip flop

Low leakage data retention flip flop

by DJAJA GREGORY, SLAMOWITZ MARK, CHANDRASEKHARAN KARTHIK
Year of Publication 15.10.2009

Get full text

Patent

Scalable Serializer

Scalable Serializer

by GORTI RAMAMURTHY, DJAJA GREGORY, CHEN HUA-FENG, CHANDRASEKHARAN KARTHIK, SMITH DOUGLAS
Year of Publication 12.12.2013

Get full text

Patent

Single stage and scalable serializer

Single stage and scalable serializer

by GORTI RAMAMURTHY, DJAJA GREGORY, CHEN HUA-FENG, CHANDRASEKHARAN KARTHIK, SMITH DOUGLAS
Year of Publication 20.08.2013

Get full text

Patent

Single Stage and Scalable Serializer

Single Stage and Scalable Serializer

by GORTI RAMAMURTHY, DJAJA GREGORY, CHEN HUA-FENG, CHANDRASEKHARAN KARTHIK, SMITH DOUGLAS
Year of Publication 29.11.2012

Get full text

Patent

CMOS Speicher(vom Mehrtorregistertyp) mit leistungsreduziertem Spaltenmultiplexierungsschema

CMOS Speicher(vom Mehrtorregistertyp) mit leistungsreduziertem Spaltenmultiplexierungsschema

by DJAJA, GREGORY, KNEBELSBERGER, DAVID W, SMITH, DOUGLAS D, SLAMOWITZ, MARK
Year of Publication 28.09.2006

Get full text

Patent

CMOS SPEICHER (VOM MEHRTOREGISTERTYP) MIT LEISTUNGSREDUZIERTEM SPALTENMULTIPLEXIERUNGSSCHEMA

CMOS SPEICHER (VOM MEHRTOREGISTERTYP) MIT LEISTUNGSREDUZIERTEM SPALTENMULTIPLEXIERUNGSSCHEMA

by DJAJA, GREGORY, KNEBELSBERGER, DAVID W, SMITH, DOUGLAS D, SLAMOWITZ, MARK
Year of Publication 15.02.2006

Get full text

Patent

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

by DJAJA, GREGORY, KNEBELSBERGER, DAVID W, SMITH, DOUGLAS D, SLAMOWITZ, MARK
Year of Publication 08.02.2006

Get full text

Patent

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

by Slamowitz, Mark, Smith, Douglas D, Knebelsberger, David W, Djaja, Gregory
Year of Publication 07.06.2005

Get full text

Patent

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

Very small swing high performance CMOS static memory (multi-port register file) with power reducing column multiplexing scheme

by KNEBELSBERGER DAVID W, DJAJA GREGORY, SLAMOWITZ MARK, SMITH DOUGLAS D
Year of Publication 07.06.2005

Get full text

Patent