FINFET technology featuring high mobility SiGe channel for 10nm and beyond
Guo, D., Karve, G., Tsutsui, G., Lim, K.-Y, Robison, R., Hook, T., Vega, R., Liu, D., Bedell, S., Mochizuki, S., Lie, F., Akarvardar, K., Wang, M., Bao, R., Burns, S., Chan, V., Cheng, K., Demarest, J., Fronheiser, J., Hashemi, P., Kelly, J., Li, J., Loubet, N., Montanini, P., Sahu, B., Sankarapandian, M., Sieg, S., Sporre, J., Strane, J., Southwick, R., Tripathi, N., Venigalla, R., Wang, J., Watanabe, K., Yeung, C. W., Gupta, D., Doris, B., Felix, N., Jacob, A., Jagannathan, H., Kanakasabapathy, S., Mo, R., Narayanan, V., Sadana, D., Oldiges, P., Stathis, J., Yamashita, T., Paruchuri, V., Colburn, M., Knorr, A., Divakaruni, R., Bu, H., Khare, M.
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
Published in 2016 IEEE Symposium on VLSI Technology (01.06.2016)
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Conference Proceeding
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
Loubet, N., Kal, S., Alix, C., Pancharatnam, S., Zhou, H., Durfee, C., Belyansky, M., Haller, N., Watanabe, K., Devarajan, T., Zhang, J., Miao, X., Sankar, M., Breton, M., Chao, R., Greene, A., Yu, L., Frougier, J., Chanemougame, D., Tapily, K., Smith, J., Basker, V., Mosden, A., Biolsi, P., Hurd, T. Q., Divakaruni, R., Haran, B., Bu, H.
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
Cheng, K., Seo, S., Faltermeier, J., Lu, D., Standaert, T., Ok, I., Khakifirooz, A., Vega, R., Levin, T., Li, J., Demarest, J., Surisetty, C., Song, D., Utomo, H., Chao, R., He, H., Madan, A., DeHaven, P., Klymko, N., Zhu, Z., Naczas, S., Yin, Y., Kuss, J., Jacob, A., Bae, D., Seo, K., Kleemeier, W., Sampson, R., Hook, T., Haran, B., Gifford, G., Gupta, D., Shang, H., Bu, H., Na, M., Oldiges, P., Wu, T., Doris, B., Rim, K., Nowak, E., Divakaruni, R., Khare, M.
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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Conference Proceeding
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
Zhang, J., Frougier, J., Greene, A., Miao, X., Yu, L., Vega, R., Montanini, P., Durfee, C., Gaul, A., Pancharatnam, S., Adams, C., Wu, H., Zhou, H., Shen, T., Xie, R., Sankarapandian, M., Wang, J., Watanabe, K., Bao, R., Liu, X., Park, C., Shobha, H., Joseph, P., Kong, D., De La Pena, A. Arceo, Li, J., Conti, R., Dechene, D., Loubet, N., Chao, R., Yamashita, T., Robison, R., Basker, V., Zhao, K., Guo, D., Haran, B., Divakaruni, R., Bu, H.
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01.12.2019)
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Conference Proceeding
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
Jagannathan, H., Anderson, B., Sohn, C-W., Tsutsui, G., Strane, J., Xie, R., Fan, S., Kim, K-I., Song, S., Sieg, S., Seshadri, I., Mochizuki, S., Wang, J., Rahman, A., Cheon, K-Y., Hwang, I., Demarest, J., Do, J., Fullam, J., Jo, G., Hong, B., Jung, Y., Kim, M., Kim, S., Lallement, R., Levin, T., Li, J., Miller, E., Montanini, P., Pujari, R., Osborn, C., Sankarapandian, M., Son, G-H., Waskiewicz, C., Wu, H., Yim, J., Young, A., Zhang, C., Varghese, A., Robison, R., Burns, S., Zhao, K., Yamashita, T., Dechene, D., Guo, D., Divakaruni, R., Wu, T., Seo, K-I., Bu, H.
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
Published in 2021 IEEE International Electron Devices Meeting (IEDM) (11.12.2021)
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Conference Proceeding
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
Tsutsui, G., Song, S., Strane, J., Xie, R., Qin, L., Zhang, C., Schmidt, D., Fan, S., Hong, B., Jung, Y., Sohn, C-W., Hwang, I., Yim, J., Son, G. H., Jo, G., Kim, K-I., Sankarapandian, M., Mochizuki, S., Seshadri, I., Miller, E., Li, J., Demarest, J., Waskiewicz, C., Southwick, R. G., Zhou, H., Pujari, R. N., Nieves, P., Wang, M., Jagannathan, H., Anderson, B., Guo, D., Divakaruni, R., Wu, T., Seo, K-I., Bu, H.
Published in 2022 International Electron Devices Meeting (IEDM) (03.12.2022)
Published in 2022 International Electron Devices Meeting (IEDM) (03.12.2022)
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Conference Proceeding
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
Beintner, J., Li, Y., Knorr, A., Chidambarrao, D., Voigt, P., Divakaruni, R., Pochmuller, P., Bronner, G.
Published in IEEE electron device letters (01.05.2004)
Published in IEEE electron device letters (01.05.2004)
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Journal Article
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Loubet, N., Hook, T., Montanini, P., Yeung, C-W, Kanakasabapathy, S., Guillom, M., Yamashita, T., Zhang, J., Miao, X., Wang, J., Young, A., Chao, R., Kang, M., Liu, Z., Fan, S., Hamieh, B., Sieg, S., Mignot, Y., Xu, W., Seo, S-C, Yoo, J., Mochizuki, S., Sankarapandian, M., Kwon, O., Carr, A., Greene, A., Park, Y., Frougier, J., Galatage, R., Bao, R., Shearer, J., Conti, R., Song, H., Lee, D., Kong, D., Xu, Y., Arceo, A., Bi, Z., Xu, P., Muthinti, R., Li, J., Wong, R., Brown, D., Oldiges, P., Robison, R., Arnold, J., Felix, N., Skordas, S., Gaudiello, J., Standaert, T., Jagannathan, H., Corliss, D., Na, M-H, Knorr, A., Wu, T., Gupta, D., Lian, S., Divakaruni, R., Gow, T., Labelle, C., Lee, S., Paruchuri, V., Bu, H., Khare, M.
Published in 2017 Symposium on VLSI Technology (01.06.2017)
Published in 2017 Symposium on VLSI Technology (01.06.2017)
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Conference Proceeding
Activation energy determination from low-temperature CV dispersion [semiconductor devices]
Divakaruni, R., Prabhakar, V., Viswanathan, C.R.
Published in IEEE transactions on electron devices (01.08.1994)
Published in IEEE transactions on electron devices (01.08.1994)
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Journal Article
On the retention time distribution of dual-channel vertical DRAM technologies
Beintner, J., Li, Y., Casarotto, D., Chidambarrao, D., McStay, K., Wang, G., Hummler, K., Divakaruni, R., Bergner, W., Crabbe, E., Mueller, W., Poechmueller, P., Bronner, G.
Published in 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672) (2003)
Published in 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672) (2003)
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Conference Proceeding
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Seo, K.-I, Haran, B., Gupta, D., Guo, D., Standaert, T., Xie, R., Shang, H., Alptekin, E., Bae, D.-I, Bae, G., Boye, C., Cai, H., Chanemougame, D., Chao, R., Cheng, K., Cho, J., Choi, K., Hamieh, B., Hong, J. G., Hook, T., Jang, L., Jung, J., Jung, R., Lee, D., Lherron, B., Kambhampati, R., Kim, B., Kim, H., Kim, K., Kim, T. S., Ko, S.-B, Lie, F. L., Liu, D., Mallela, H., Mclellan, E., Mehta, S., Montanini, P., Mottura, M., Nam, J., Nam, S., Nelson, F., Ok, I., Park, C., Park, Y., Paul, A., Prindle, C., Ramachandran, R., Sankarapandian, M., Sardesai, V., Scholze, A., Seo, S.-C, Shearer, J., Southwick, R., Sreenivasan, R., Stieg, S., Strane, J., Sun, X., Sung, M. G., Surisetty, C., Tsutsui, G., Tripathi, N., Vega, R., Waskiewicz, C., Weybright, M., Yeh, C.-C, Bu, H., Burns, S., Canaperi, D., Celik, M., Colburn, M., Jagannathan, H., Kanakasabaphthy, S., Kleemeier, W., Liebmann, L., Mcherron, D., Oldiges, P., Paruchuri, V., Spooner, T., Stathis, J., Divakaruni, R., Gow, T., Iacoponi, J., Jenq, J., Sampson, R., Khare, M.
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
Published in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers (01.06.2014)
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Conference Proceeding
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
KAWANAKA, S, KETCHEN, M. B, NII, H, HARIFUCHI, H, SUDO, G, RAUSCH, W, KIMURA, H, NAKAO, T, PARK, H, OH, S.-H, WAITE, A, WOMACK, S, BHUSHAN, M, NARASIMHA, S, MOCUTA, A. C, AJMERA, A, LI, Y, MALIK, R, KOHYAMA, Y, CHEEK, J, YANG, I, CLARK, W. F, DIVAKARUNI, R, PEARSON, D. J, BHASIN, R, MCSTAY, K, SHERONY, M, FISHER, P, MATSUMOTO, K, UTOMO, H
Year of Publication 2004
Year of Publication 2004
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Conference Proceeding
Low-temperature CV dispersion in MOS devices
Viswanathan, C.R., Divakaruni, R., Kizziar, J.
Published in IEEE electron device letters (01.09.1991)
Published in IEEE electron device letters (01.09.1991)
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Journal Article
Nitride framed shallow trench isolation (NFSTI) for self-aligned buried strap in high performance trench capacitor DRAM/eDRAM
Kim, B., Fukuzaki, Y., Worth, G., Nuetzel, J., Williams, G., Lee, B., Takegawa, Y., Halle, S., Rupp, T., Sudo, A., Divakaruni, R., Srinivasan, R., Mii, T., Bronner, G.
Published in 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) (2001)
Published in 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) (2001)
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