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7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
Barraud, S., Previtali, B., Vizioz, C., Hartmann, J. M., Sturm, J., Lassarre, J., Perrot, C., Rodriguez, Ph, Loup, V., Magalhaes-Lucas, A., Kies, R., Romano, G., Casse, M., Bernier, N., Jannaud, A., Grenier, A., Andrieu, F.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
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A copper ReRAM cell for Storage Class Memory applications
Sills, Scott, Yasuda, Shuichiro, Strand, Jonathan, Calderoni, Alessandro, Aratani, Katsuhisa, Johnson, Adam, Ramaswamy, Nirmal
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2014)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2014)
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Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics
Bardon, M. Garcia, Raghavan, P., Eneman, G., Schuddinck, P., Dehan, M., Mercha, A., Thean, A., Verkest, D., Steegen, A.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2014)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2014)
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Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Loubet, N., Hook, T., Montanini, P., Yeung, C-W, Kanakasabapathy, S., Guillom, M., Yamashita, T., Zhang, J., Miao, X., Wang, J., Young, A., Chao, R., Kang, M., Liu, Z., Fan, S., Hamieh, B., Sieg, S., Mignot, Y., Xu, W., Seo, S-C, Yoo, J., Mochizuki, S., Sankarapandian, M., Kwon, O., Carr, A., Greene, A., Park, Y., Frougier, J., Galatage, R., Bao, R., Shearer, J., Conti, R., Song, H., Lee, D., Kong, D., Xu, Y., Arceo, A., Bi, Z., Xu, P., Muthinti, R., Li, J., Wong, R., Brown, D., Oldiges, P., Robison, R., Arnold, J., Felix, N., Skordas, S., Gaudiello, J., Standaert, T., Jagannathan, H., Corliss, D., Na, M-H, Knorr, A., Wu, T., Gupta, D., Lian, S., Divakaruni, R., Gow, T., Labelle, C., Lee, S., Paruchuri, V., Bu, H., Khare, M.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2017)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2017)
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SoC Compatible 1T1C FeRAM Memory Array Based on Ferroelectric Hf0.5Zr0.5O2
Okuno, Jun, Kunihiro, Takafumi, Konishi, Kenta, Maemura, Hideki, Shuto, Yusuke, Sugaya, Fumitaka, Materano, Monica, Ali, Tarek, Kuehnel, Kati, Seidel, Konrad, Schroeder, Uwe, Mikolajick, Thomas, Tsukamoto, Masanori, Umebayashi, Taku
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
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Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET
Kobayashi, M., Kinoshita, A., Saraswat, K., Wong, H.-S.P., Nishi, Y.
Published in 2008 Symposium on VLSI Technology (01.06.2008)
Published in 2008 Symposium on VLSI Technology (01.06.2008)
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Novel ferroelectric FET based synapse for neuromorphic systems
Mulaosmanovic, H., Ocker, J., Muller, S., Noack, M., Muller, J., Polakowski, P., Mikolajick, T., Slesazeck, S.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2017)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2017)
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A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs
Ni, Kai, Jerry, Matthew, Smith, Jeffrey A., Datta, Suman
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology
De, Sourav, Lu, Darsen D., Le, Hoang-Hiep, Mazumder, Soumen, Lee, Yao-Jen, Tseng, Wei-Chih, Qiu, Bo-Han, Baig, Md. Aftab, Sung, Po-Jung, Su, Chung-Jun, Wu, Chien-Ting, Wu, Wen-Fa, Yeh, Wen-Kuan, Wang, Yeong-Her
Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
Mertens, H., Ritzenthaler, R., Oniki, Y., Briggs, B., Chan, B.T., Hikavyy, A., Hopf, T., Mannaert, G., Tao, Z., Sebaai, F., Peter, A., Vandersmissen, K., Dupuy, E., Rosseel, E., Batuk, D., Geypen, J., Martinez, G. T., Abigail, D., Grieten, E., Dehave, K., Mitard, J., Subramanian, S., Ragnarsson, L.-A., Weckx, P., Jang, D., Chehab, B., Hellings, G., Ryckaert, J., Litta, E. Dentoni, Horiguchi, N.
Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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The Complementary FET (CFET) for CMOS scaling beyond N3
Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., Bao, T. Huynh, Veloso, A., Horiguchi, N., Mocuta, A., Mocuta, D., Boemmels, J.
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture
Mochida, Reiji, Kouno, Kazuyuki, Hayata, Yuriko, Nakayama, Masayoshi, Ono, Takashi, Suwa, Hitoshi, Yasuhara, Ryutaro, Katayama, Koji, Mikawa, Takumi, Gohou, Yasushi
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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A Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing
Wu, Wei, Wu, Huaqiang, Gao, Bin, Yao, Peng, Zhang, Xiang, Peng, Xiaochen, Yu, Shimeng, Qian, He
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
Published in 2018 IEEE Symposium on VLSI Technology (01.06.2018)
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Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM
Garello, K., Yasin, F., Hody, H., Couet, S., Souriau, L., Sharifi, S. H., Swerts, J., Carpenter, R., Rao, S., Kim, W., Wu, J., Sethu, K.K.V., Pak, M., Jossart, N., Crotti, D., Furnemont, A., Kar, G. S.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
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RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation
Yan, Bonan, Yang, Qing, Chen, Wei-Hao, Chang, Kung-Tang, Su, Jian-Wei, Hsu, Chien-Hua, Li, Sih-Han, Lee, Heng-Yuan, Sheu, Shyh-Shyuan, Ho, Mon-Shu, Wu, Qing, Chang, Meng-Fan, Chen, Yiran, Li, Hai
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
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FeFET Memory Featuring Large Memory Window and Robust Endurance of Long-Pulse Cycling by Interface Engineering using High-k AlON
Chan, Chi-Yu, Chen, Kuen-Yi, Peng, Hao-Kai, Wu, Yung-Hsien
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2020)
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First demonstration of sub-12 nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices
Subhechha, S., Rassoul, N., Belmonte, A., Delhougne, R., Banerjee, K., Donadio, G. L., Dekkers, H., van Setten, M. J., Puliyalil, H., Mao, M., Kundu, S., Pak, M., Teugels, L., Tsvetanova, D., Bazzazian, N., Klijs, L., Hody, H., Chasin, A., Heijlen, J., Goux, L., Kar, G. S.
Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Non-Volatile RRAM Embedded into 22FFL FinFET Technology
Golonzka, O., Arslan, U., Bai, P., Bohr, M., Baykan, O., Chang, Y., Chaudhari, A., Chen, A., Clarke, J., Connor, C., Das, N., English, C., Ghani, T., Hamzaoglu, F., Hentges, P., Jain, P., Jezewski, C., Karpov, I., Kothari, H., Kotlyar, R., Lin, B., Metz, M., Odonnell, J., Ouellette, D., Park, J., Pirkle, A., Quintero, P., Seghete, D., Sekhar, M., Gupta, A. Sen, Seth, M., Strutt, N., Wiegand, C., Yoo, H. J., Fischer, K.
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
Published in Digest of technical papers - Symposium on VLSI Technology (01.06.2019)
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Characterization of Fatigue and Its Recovery Behavior in Ferroelectric HfZrO
Liao, P.J., Chang, Y.K., Lee, Y.-H., Lin, Y.M., Yeong, S.H., Hwang, R.L., Hou, V., Nien, C.H., Lu, R., Lin, C.T.
Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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Published in Digest of technical papers - Symposium on VLSI Technology (13.06.2021)
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A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
Auth, C., Allen, C., Blattner, A., Bergstrom, D., Brazier, M., Bost, M., Buehler, M., Chikarmane, V., Ghani, T., Glassman, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., Hentges, P., Heussner, R., Hicks, J., Ingerly, D., Jain, P., Jaloviar, S., James, R., Jones, D., Jopling, J., Joshi, S., Kenyon, C., Liu, H., McFadden, R., McIntyre, B., Neirynck, J., Parker, C., Pipes, L., Post, I., Pradhan, S., Prince, M., Ramey, S., Reynolds, T., Roesler, J., Sandford, J., Seiple, J., Smith, P., Thomas, C., Towner, D., Troeger, T., Weber, C., Yashar, P., Zawadzki, K., Mistry, K.
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
Published in 2012 Symposium on VLSI Technology (VLSIT) (01.06.2012)
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