5nm-gate nanowire FinFET
Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
Modeling isolation-induced mechanical stress effect on SOI MOS devices
Ke-Wei Su, Kuang-Hsin Chen, Tang-Xuan Chung, Hung-Wei Chen, Cheng-Chuan Huang, Hou-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Cheng-Kuo Wen, Yi-Ming Sheu, Sheng-Jier Yang, Chung-Shi Chiang, Chien-Chao Huang, Fu-Liang Yang, Yu-Tai Chia
Published in 2003 IEEE International Conference on SOI (2003)
Published in 2003 IEEE International Conference on SOI (2003)
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Conference Proceeding
A 1.2-volt operation power PHEMT for personal handy phone handset application
Chang, E.Y., Di-Hong Lee, Chen, S.H.
Published in 2000 Asia-Pacific Microwave Conference. Proceedings (Cat. No.00TH8522) (2000)
Published in 2000 Asia-Pacific Microwave Conference. Proceedings (Cat. No.00TH8522) (2000)
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Conference Proceeding
Semiconductor nano-wire devices and methods of fabrication
Chen, Hung-Wei, Yeo, Yee-Chia, Lee, Di-Hong, Yang, Fu-Liang, Hu, Chenming
Year of Publication 18.11.2008
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Year of Publication 18.11.2008
Patent
Semiconductor device employing an extension spacer and a method of forming the same
Chen, Kuang-Hsin, Zhong, Tang-Xuan, Huang, Chien-Chao, Wen, Cheng-Kuo, Lee, Di-Hong
Year of Publication 04.09.2007
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Year of Publication 04.09.2007
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FIN-FET device structure formed employing bulk semiconductor substrate
Chen, Kuang-Hsin, Tsao, Hsun-Chih, Lu, Jhi-Cherng, Hou, Chuan-Ping, Hsu, Peng-Fu, Chen, Hung-Wei, Lee, Di-Hong
Year of Publication 16.02.2010
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Year of Publication 16.02.2010
Patent
STI liner for SOI structure
Chen, Kuang-Hsin, Tsao, Hsun-Chih, Chen, Hung-Wei, Lee, Di-Hong, Hou, Chuan-Ping, Lu, Jhi-Cherng
Year of Publication 19.02.2008
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Year of Publication 19.02.2008
Patent
STI liner for SOI structure
Chen, Kuang-Hsin, Tsao, Hsun-Chih, Chen, Hung-Wei, Lee, Di-Hong, Hou, Chuan-Ping, Lu, Jhi-Cherng
Year of Publication 18.10.2005
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Year of Publication 18.10.2005
Patent
5nm-Gate nanowire FinFET
YANG, Fu-Liang, LEE, Di-Hong, WU, Chung-Cheng, CHEN, Chi-Chun, CHEN, Shih-Chang, CHEN, Ying-Tsung, CHEN, Ying-Ho, CHEN, Chih-Jian, CHAN, Bor-Wen, HSU, Peng-Fu, SHIEH, Jyu-Homg, TAO, Han-Jan, CHEN, Hou-Yu, YEO, Yee-Chia, YIMING LI, LEE, Jam-Wem, PU CHEN, LIANG, Mong-Song, CHENMING HU, CHANG, Chang-Yun, LIU, Sheng-Da, HUANG, Cheng-Chuan, CHUNG, Tang-Xuan, CHEN, Hung-Wei, HUANG, Chien-Chao, LIU, Yi-Hsuan
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Conference Proceeding
45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell
YANG, Fu-Liang, HUANG, Cheng-Chuan, WEN, Cheng-Kuo, CHENG, Shui-Ming, YANG, Chang-Ta, KUNG, Li-Wei, LEE, Chiu-Lien, CHOU, Yu-Jun, LIANG, Fu-Jye, SHIU, Lin-Hung, YOU, Jan-Wen, SHU, King-Chang, HUANG, Chien-Chao, CHANG, Bin-Chang, SHIN, Jaw-Jung, CHEN, Chun-Kuang, GAU, Tsai-Sheng, WANG, Ping-Wei, CHAN, Bor-Wen, HSU, Peng-Fu, SHIEH, Jyu-Horng, FUNG, Samuel K.-H, DIAZ, Carlos H, CHUNG, Tang-Xuan, WU, Chii-Ming M, SEE, Yee-Chaung, LIN, Burn J, LIANG, Mong-Song, SUN, Jack Y.-C, CHENMING HU, CHEN, Hou-Yu, CHANG, Chang-Yun, CHEN, Hung-Wei, LEE, Di-Hong, LIU, Sheng-Da, CHEN, Kuang-Hsin
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Conference Proceeding
45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell
Fu-Liang Yang, Cheng-Chuan Huang, Chien-Chao Huang, Tang-Xuan Chung, Hou-Yu Chen, Chang-Yun Chang, Hung-Wei Chen, Di-Hong Lee, Sheng-Da Liu, Kuang-Hsin Chen, Cheng-Kuo Wen, Shui-Ming Cheng, Chang-Ta Yang, Li-Wei Kung, Chiu-Lien Lee, Yu-Jun Chou, Fu-Jye Liang, Lin-Hung Shiu, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Ping-Wei Wang, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Honig Shieh, Fung, S.K.-H., Diaz, C.H., Wu, C.-M.M., Yee-Chaung See, Lin, B.J., Liang, M.-S., Sun, J.Y.-C., Chenming Hu
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
Published in Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004 (2004)
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Conference Proceeding
A 65nm node strained SOI technology with slim spacer
Fu-Liang Yang, Chien-Chao Huang, Hou-Yu Chen, Jhon-Jhy Liaw, Tang-Xuan Chung, Hung-Wei Chen, Chang-Yun Chang, Cheng Chuan Huang, Kuang-Hsin Chen, Di-Hong Lee, Hsun-Chih Tsao, Cheng-Kuo Wen, Shui-Ming Cheng, Yi-Ming Sheu, Ke-Wei Su, Chi-Chun Chen, Tze-Liang Lee, Shih-Chang Chen, Chih-Jian Chen, Cheng-hung Chang, Jhi-cheng Lu, Weng Chang, Chuan-Ping Hou, Ying-Ho Chen, Kuei-Shun Chen, Ming Lu, Li-Wei Kung, Yu-Jun Chou, Fu-Jye Liang, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Bor-Wen Chan, Yi-Chun Huang, Han-Jan Tao, Jyh-Huei Chen, Yung-Shun Chen, Yee-Chia Yeo, Fung, S.K.-H., Diaz, C.H., Wu, C.-M.M., Lin, B.J., Liang, M.-S., Sun, J.Y.-C., Chenming Hu
Published in IEEE International Electron Devices Meeting 2003 (2003)
Published in IEEE International Electron Devices Meeting 2003 (2003)
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Conference Proceeding
Semiconductor device employing an extension spacer and a method of forming the same
WEN CHENG-KUO, HUANG CHIENAO, CHEN KUANG-HSIN, ZHONG TANG-XUAN, LEE DI-HONG
Year of Publication 04.09.2007
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Year of Publication 04.09.2007
Patent