FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Cassé, M., Allain, F., Loubet, N., Pham-Nguyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Thin-film devices for low power applications
Monfray, S., Fenouillet-Beranger, C., Bidal, G., Boeuf, F., Denorme, S., Huguenin, J.L., Samson, M.P., Loubet, N., Hartmann, J.M., Campidelli, Y., Destefanis, V., Arvet, C., Benotmane, K., Clement, L., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.02.2010)
Published in Solid-state electronics (01.02.2010)
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Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
Fenouillet-Beranger, C, Thomas, O, Perreau, P, Noel, J.-P, Bajolet, A, Haendler, S, Tosti, L, Barnola, S, Beneyton, R, Perrot, C, de Buttet, C, Abbate, F, Baron, F, Pernet, B, Campidelli, Y, Pinzelli, L, Gouraud, P, Cassé, M, Borowiak, C, Weber, O, Andrieu, F, Denorme, S, Boeuf, F, Faynot, O, Skotnicki, T, Bourdelle, K K, Nguyen, B Y, Boedt, F
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Gate-all-around technology: Taking advantage of ballistic transport?
Huguenin, J.L., Bidal, G., Denorme, S., Fleury, D., Loubet, N., Pouydebasque, A., Perreau, P., Leverd, F., Barnola, S., Beneyton, R., Orlando, B., Gouraud, P., Salvetat, T., Clement, L., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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Silicon MOSFETs as room temperature terahertz detectors
Videlier, H, Nadar, S, Dyakonova, N, Sakowicz, M, Dam, T Trinh Van, Teppe, F, Coquillat, D, Knap, W, Denorme, S, Skotnicki, T, Peiris, J M, Lyonnet, J
Published in Journal of physics. Conference series (01.11.2009)
Published in Journal of physics. Conference series (01.11.2009)
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Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution
Bidal, G., Loubet, N., Fenouillet-Beranger, C., Denorme, S., Perreau, P., Fleury, D., Clement, L., Laviron, C., Leverd, F., Gouraud, P., Barnola, S., Beneyton, R., Torres, A., Duluard, C., Chapon, J.D., Orlando, B., Salvetat, T., Grosjean, M., Deloffre, E., Pantel, R., Dutartre, D., Monfray, S., Ghibaudo, G., Boeuf, F., Skotnicki, T.
Published in Solid-state electronics (01.07.2009)
Published in Solid-state electronics (01.07.2009)
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High-Performance High- K/Metal Planar Self-Aligned Gate-All-Around CMOS Devices
Pouydebasque, A., Denorme, S., Loubet, N., Wacquez, R., Bustos, J., Leverd, F., Deloffre, E., Barnola, S., Dutartre, D., Coronel, P., Skotnicki, T.
Published in IEEE transactions on nanotechnology (01.09.2008)
Published in IEEE transactions on nanotechnology (01.09.2008)
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Journal Article
Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below
Fenouillet-Beranger, C., Perreau, P., Denorme, S., Tosti, L., Andrieu, F., Weber, O., Monfray, S., Barnola, S., Arvet, C., Campidelli, Y., Haendler, S., Beneyton, R., Perrot, C., de Buttet, C., Gros, P., Pham-Nguyen, L., Leverd, F., Gouraud, P., Abbate, F., Baron, F., Torres, A., Laviron, C., Pinzelli, L., Vetier, J., Borowiak, C., Margain, A., Delprat, D., Boedt, F., Bourdelle, K., Nguyen, B.-Y., Faynot, O., Skotnicki, T.
Published in Solid-state electronics (01.09.2010)
Published in Solid-state electronics (01.09.2010)
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New insight on VT stability of HK/MG stacks with scaling in 30nm FDSOI technology
Brunet, L, Garros, X, Cassé, M, Weber, O, Andrieu, F, Fenouillet-Béranger, C, Perreau, P, Martin, F, Charbonnier, M, Lafond, D, Gaumer, C, Lhostis, S, Vidal, V, Brevard́, L, Tosti, L, Denorme, S, Barnola, S, Damlencourt, J F, Loup, V, Reimbold, G, Boulanger, F, Faynot, O, Bravaix, A
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Endurance/Retention Trade Off in HfOx and TaOx Based RRAM
Azzaz, M., Vianello, E., Sklenard, B., Blaise, P., Roule, A., Sabbione, C., Bernasconi, S., Charpin, C., Cagli, C., Jalaguier, E., Jeannot, S., Denorme, S., Candelier, P., Yu, M., Nistor, L., Fenouillet-Beranger, C., Perniola, L.
Published in 2016 IEEE 8th International Memory Workshop (IMW) (01.05.2016)
Published in 2016 IEEE 8th International Memory Workshop (IMW) (01.05.2016)
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Conference Proceeding
Hybrid Localized SOI/bulk technology for low power system-on-chip
Huguenin, J.-L, Monfray, S, Bidal, G, Denorme, S, Perreau, P, Barnola, S, Samson, M.-P, Arvet, C, Benotmane, K, Loubet, N, Liu, Q, Campidelli, Y, Leverd, F, Abbate, F, Clement, L, Borowiak, C, Cros, A, Bajolet, A, Handler, S, Marin-Cudraz, D, Benoist, T, Galy, P, Fenouillet-Beranger, C, Faynot, O, Ghibaudo, G, Boeuf, F, Skotnicki, T
Published in 2010 Symposium on VLSI Technology (01.06.2010)
Published in 2010 Symposium on VLSI Technology (01.06.2010)
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Conference Proceeding
Improvement of performances HfO 2 -based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al 2 O 3
Azzaz, M., Benoist, A., Vianello, E., Garbin, D., Jalaguier, E., Cagli, C., Charpin, C., Bernasconi, S., Jeannot, S., Dewolf, T., Audoit, G., Guedj, C., Denorme, S., Candelier, P., Fenouillet-Beranger, C., Perniola, L.
Published in Solid-state electronics (01.11.2016)
Published in Solid-state electronics (01.11.2016)
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Improvement of performances HfO2-based RRAM from elementary cell to 16kb demonstrator by introduction of thin layer of Al2O3
Azzaz, M., Benoist, A., Vianello, E., Garbin, D., Jalaguier, E., Cagli, C., Charpin, C., Bernasconi, S., Jeannot, S., Dewolf, T., Audoit, G., Guedj, C., Denorme, S., Candelier, P., Fenouillet-Beranger, C., Perniola, L.
Published in Solid-state electronics (01.11.2016)
Published in Solid-state electronics (01.11.2016)
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Effect of SET temperature on data retention performances of HfO2-based RRAM cells
Cabout, T., Vianello, E., Jalaguier, E., Grampeix, H., Molas, G., Blaise, P., Cueto, O., Guillermet, M., Nodin, J. F., Pemiola, L., Blonkowski, S., Jeannot, S., Denorme, S., Candelier, P., Bocquet, M., Muller, C.
Published in 2014 IEEE 6th International Memory Workshop (IMW) (01.05.2014)
Published in 2014 IEEE 6th International Memory Workshop (IMW) (01.05.2014)
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Conference Proceeding
28nm advanced CMOS resistive RAM solution as embedded non-volatile memory
Benoist, A., Blonkowski, S., Jeannot, S., Denorme, S., Damiens, J., Berger, J., Candelier, P., Vianello, E., Grampeix, H., Nodin, J. F., Jalaguier, E., Perniola, L., Allard, B.
Published in 2014 IEEE International Reliability Physics Symposium (01.06.2014)
Published in 2014 IEEE International Reliability Physics Symposium (01.06.2014)
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Conference Proceeding
Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology
Benoist, A., Denorme, S., Federspiel, X., Allard, B., Candelier, P.
Published in 2015 IEEE International Reliability Physics Symposium (01.04.2015)
Published in 2015 IEEE International Reliability Physics Symposium (01.04.2015)
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Conference Proceeding
Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization
Azzaz, M., Benoist, A., Vianello, E., Garbin, D., Jalaguier, E., Cagli, C., Charpin, C., Bernasconi, S., Jeannot, S., Dewolf, T., Audoit, G., Guedj, C., Denorme, S., Candelier, P., Fenouillet-Beranger, C., Perniola, L.
Published in 2015 45th European Solid State Device Research Conference (ESSDERC) (01.09.2015)
Published in 2015 45th European Solid State Device Research Conference (ESSDERC) (01.09.2015)
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Conference Proceeding
A solution for an ideal planar multi-gates process for ultimate CMOS?
Monfray, S, Huguenin, J, Martin, M, Samson, M, Borowiak, C, Arvet, C, Dalemcourt, J, Perreau, P, Barnola, S, Bidal, G, Denorme, S, Campidelli, Y, Benotmane, K, Leverd, F, Gouraud, P, Le-Gratiet, B, De-Buttet, C, Pinzelli, L, Beneyton, R, Morel, T, Wacquez, R, Bustos, J, Icard, B, Pain, L, Barraud, S, Ernst, T, Boeuf, F, Faynot, O, Skotnicki, T
Published in 2010 International Electron Devices Meeting (01.12.2010)
Published in 2010 International Electron Devices Meeting (01.12.2010)
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