Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part II: Implications for Process, Device, and Circuit Design
Dadgour, Hamed F, Endo, Kazuhiko, De, Vivek K, Banerjee, Kaustav
Published in IEEE transactions on electron devices (01.10.2010)
Published in IEEE transactions on electron devices (01.10.2010)
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Journal Article
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Bowman, K.A., Tschanz, J.W., Nam Sung Kim, Lee, J.C., Wilkerson, C.B., Lu, S.-L.L., Karnik, T., De, V.K.
Published in IEEE journal of solid-state circuits (01.01.2009)
Published in IEEE journal of solid-state circuits (01.01.2009)
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Journal Article
Conference Proceeding
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance
Bowman, K. A., Tokunaga, C., Karnik, T., De, V. K., Tschanz, J. W.
Published in IEEE journal of solid-state circuits (01.04.2013)
Published in IEEE journal of solid-state circuits (01.04.2013)
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Conference Proceeding
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS
Satpathy, Sudhir, Mathew, Sanu K., Suresh, Vikram, Anders, Mark A., Kaul, Himanshu, Agarwal, Amit, Hsu, Steven K., Chen, Gregory, Krishnamurthy, Ram K., De, Vivek K.
Published in IEEE journal of solid-state circuits (01.04.2017)
Published in IEEE journal of solid-state circuits (01.04.2017)
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Journal Article
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays
Raychowdhury, Arijit, Geuskens, Bibiche M, Bowman, Keith A, Tschanz, James W, Lu, Shih-Lien L, Karnik, Tanay, Khellah, Muhammad M, De, Vivek K
Published in IEEE journal of solid-state circuits (01.04.2011)
Published in IEEE journal of solid-state circuits (01.04.2011)
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Journal Article
Conference Proceeding
Accurate Estimation of SRAM Dynamic Stability
Khalil, D.E., Khellah, M., Nam-Sung Kim, Ismail, Y., Karnik, T., De, V.K.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2008)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.2008)
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Journal Article
Variation Tolerance in a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits
Raychowdhury, A., De, V.K., Kurtin, J., Borkar, S.Y., Roy, K., Keshavarzi, A.
Published in IEEE transactions on electron devices (01.03.2009)
Published in IEEE transactions on electron devices (01.03.2009)
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Journal Article
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS
Kumar, Raghavan, Suresh, Vikram B., Anders, Mark A., Hsu, Steven K., Agarwal, Amit, De, Vivek K., Mathew, Sanu K.
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20.02.2022)
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Conference Proceeding
A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs-Part II: Implementation and Implications for Power Estimation and Thermal Management
Sheng-Chih Lin, Chrysler, G., Mahajan, R., De, V.K., Banerjee, K.
Published in IEEE transactions on electron devices (01.12.2007)
Published in IEEE transactions on electron devices (01.12.2007)
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Journal Article
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
Howard, J, Dighe, S, Vangal, S R, Ruhl, G, Borkar, N, Jain, S, Erraguntla, V, Konow, M, Riepen, M, Gries, M, Droege, G, Lund-Larsen, T, Steibl, S, Borkar, S, De, V K, Van Der Wijngaart, R
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
Bowman, K A, Tschanz, J W, Lu, S L, Aseron, P A, Khellah, M M, Raychowdhury, A, Geuskens, B M, Tokunaga, C, Wilkerson, C B, Karnik, T, De, V K
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control
Bowman, K. A., Tokunaga, C., Tschanz, J. W., Raychowdhury, A., Khellah, M. M., Geuskens, B. M., Lu, Shih-Lien L., Aseron, P. A., Karnik, T., De, V. K.
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2011)
Published in IEEE transactions on circuits and systems. I, Regular papers (01.09.2011)
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Journal Article
A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS
Kumar, Raghavan, Chen, Gregory K., Ekin Sumbul, H., Knag, Phil C., Anders, Mark A., Kaul, Himanshu, Hsu, Steven K., Agarwal, Amit, Kar, Monodeep, Kim, Seongjong, Suresh, Vikram B., Krishnamurthy, Ram K., De, Vivek K., Mathew, Sanu K.
Published in IEEE solid-state circuits letters (2020)
Published in IEEE solid-state circuits letters (2020)
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Journal Article
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor
Dighe, S, Vangal, S R, Aseron, P, Kumar, S, Jacob, T, Bowman, K A, Howard, J, Tschanz, J, Erraguntla, V, Borkar, N, De, V K, Borkar, S
Published in IEEE journal of solid-state circuits (01.01.2011)
Published in IEEE journal of solid-state circuits (01.01.2011)
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Journal Article
Conference Proceeding
Design and optimization of dual-threshold circuits for low-voltage low-power applications
Wei, L., Chen, Z., Roy, K., Johnson, M.C., Ye, Y., De, V.K.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.1999)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.03.1999)
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Journal Article
Intrinsic MOSFET parameter fluctuations due to random dopant placement
Xinghai Tang, De, V.K., Meindl, J.D.
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.1997)
Published in IEEE transactions on very large scale integration (VLSI) systems (01.12.1997)
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Conference Proceeding
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology
Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.
Published in IEEE journal of solid-state circuits (01.01.2009)
Published in IEEE journal of solid-state circuits (01.01.2009)
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Conference Proceeding
Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages
Kursun, Volkan, Narendra, Siva G., De, Vivek K., Friedman, Eby G.
Published in Analog integrated circuits and signal processing (01.03.2005)
Published in Analog integrated circuits and signal processing (01.03.2005)
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