A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Plessas, F, Davrazos, E, Alexandropoulos, A, Birbas, M, Kikidis, J
Published in Computers & electrical engineering (01.03.2012)
Published in Computers & electrical engineering (01.03.2012)
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Journal Article
Advanced calibration techniques for high-speed source―synchronous interfaces
PLESSAS, F, ALEXANDROPOULOS, A, KOUTSOMITSOS, S, DAVRAZOS, E, BIRBAS, M
Published in IET computers & digital techniques (01.09.2011)
Published in IET computers & digital techniques (01.09.2011)
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Journal Article
A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface
Alexandropoulos, A, Davrazos, E, Plessas, F, Birbas, M
Published in 2010 IEEE Computer Society Annual Symposium on VLSI (01.07.2010)
Published in 2010 IEEE Computer Society Annual Symposium on VLSI (01.07.2010)
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Conference Proceeding
A 1GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration, and slew rate control
Plessas, F., Davrazos, E., Alexandropoulos, A., Birbas, M., Kikidis, J.
Published in Computers & electrical engineering (01.03.2012)
Published in Computers & electrical engineering (01.03.2012)
Get full text
Journal Article