Search Results - "David J Sager" :: K.UTB vyhledávací portál | TBU Library Retrieval Portal

A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit

A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit

by Hinton, G., Upton, M., Sager, D.J., Boggs, D., Carmean, D.M., Roussel, P., Chappell, T.I., Fletcher, T.D., Milshtein, M.S., Sprague, M., Samaan, S., Murray, R.
Published in IEEE journal of solid-state circuits (01.11.2001)

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Journal Article

Daten-Cache mit Datenspeicherung und Tag-Logik bei unterschiedlichen Takten

Daten-Cache mit Datenspeicherung und Tag-Logik bei unterschiedlichen Takten

by SAGER, DAVID J
Year of Publication 16.07.2009

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Patent

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

by Kim, Ho-Seop, Ngai, Tin-Fook, Sasanka, Ruchira, Raikin, Shlomo, Peled, Leeor, Yamada, Koichi, Domer, Jason A, Chen, Howard H, Shaikh, Omar M, Sager, David J, Wu, Youfeng, Nuzman, Joseph, Gabor, Ron, Bobba, Jayaram, Cook, Jeffrey J, Srinivas, Suresh
Year of Publication 28.07.2020

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Patent

Using control flow data structures to direct and track instruction execution

Using control flow data structures to direct and track instruction execution

by Bobba Jayaram, Krishnaswamy Arvind, Sasanka Ruchira, Das Abhinav, Sager David J, Cook Jeffrey J, Agron Jason M
Year of Publication 30.01.2018

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Patent

Method for a hardware and software system to automatically decompose a program to multiple parallel threads

Method for a hardware and software system to automatically decompose a program to multiple parallel threads

by Howard H Chen, Joseph Nuzman, David J Sager, Jeffrey J Cook, Ho-Seop Kim, Youfeng Wu, Jayaram Bobba, Jason A Domer, Ron Gabor, Koichi Yamada, Tin-Fook Ngai, Ruchira Sasanka, Suresh Srinivas, Shlomo Raikin, Osmar M Shaikh, Leeor Peled
Year of Publication 11.12.2019

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Patent

CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATA

CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATA

by SAGER, DAVID, J
Year of Publication 20.12.2006

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Patent

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

by SAGER DAVID J
Year of Publication 29.08.2006

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Patent

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

by Sager, David J
Year of Publication 29.08.2006

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Patent

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

by BOBBA JAYARAM, KRISHNASWAMY ARVIND, SASANKA RUCHIRA, COOK JEFFREY J, DAS ABHINAV, SAGER DAVID J, SRINIVAS SURESH
Year of Publication 17.11.2015

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Patent

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

by Sager, David J
Year of Publication 09.08.2005

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Patent

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

by SAGER DAVID J
Year of Publication 09.08.2005

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Patent

Content addressable memory addressable by redundant form input data

Content addressable memory addressable by redundant form input data

by SAGER, DAVID, J
Year of Publication 29.04.2005

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Patent

Processor having execution core sections operating at different clock rates

Processor having execution core sections operating at different clock rates

by UPTON MICHAEL D, SAGER DAVID J, HINTON GLENN J, FLETCHER THOMAS D
Year of Publication 21.04.2015

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Patent

REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM

REDUNDANT FORM ADDRESS DECODER FOR MEMORY SYSTEM

by SAGER, DAVID, J
Year of Publication 24.11.2004

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Patent

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

by DAVID J SAGER
Year of Publication 07.07.2004

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Patent

CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATA

CONTENT ADDRESSABLE MEMORY ADDRESSABLE BY REDUNDANT FORM INPUT DATA

by SAGER, DAVID, J
Year of Publication 16.06.2004

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Patent

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

by DAVID J SAGER
Year of Publication 07.04.2004

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Patent

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies

by SAGER DAVID J
Year of Publication 29.01.2004

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Patent

Method and apparatus for assigning thread priority in a processor or the like

Method and apparatus for assigning thread priority in a processor or the like

by UPTON MICHAEL D, ALLEN JAMES D, BURNS DAVID W, BOGGS DARRELL D, SAGER DAVID J
Year of Publication 30.09.2014

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Patent

Tracking control flow of instructions

Tracking control flow of instructions

by JAYARAM BOBBA, DAVID J SAGER, JASON M AGRON, ARVIND KRISHNASWAMY, ABHINAV DAS, RUCHIRA SASANKA, JEFFREY J COOK
Year of Publication 21.10.2015

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Patent

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