A 22nm IA multi-CPU and GPU System-on-Chip
Damaraju, S., George, V., Jahagirdar, S., Khondker, T., Milstrey, R., Sarkar, S., Siers, S., Stolero, I., Subbiah, A.
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
Published in 2012 IEEE International Solid-State Circuits Conference (01.02.2012)
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Conference Proceeding
Penryn: 45-nm next generation Intel® core™ 2 processor
Varghese George, Sanjeev Jahagirdar, Chao Tong, Smits, Ken, Satish Damaraju, Siers, Scott, Ves Naydenov, Tanveer Khondker, Sanjib Sarkar, Puneet Singh
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
Published in 2007 IEEE Asian Solid-State Circuits Conference (01.11.2007)
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Conference Proceeding
DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS
KOKER ALTUG, NAVALE ADITYA, DAMARAJU SATISH K, SHAH SHAILESH, RAMADOSS MURALI
Year of Publication 27.06.2014
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Year of Publication 27.06.2014
Patent
Multibit vectored sequential with scan
Damaraju, Satish, Agarwal, Amit, Hsu, Steven, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 13.09.2022
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Year of Publication 13.09.2022
Patent
Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop
Damaraju, Satish, Hsu, Steven, Agarwal, Amit, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 26.07.2022
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Year of Publication 26.07.2022
Patent
SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS FOR ZETTA-SCALE INTEGRATED CIRCUITS
Kokar, Altug, Damaraju, Satish, Siers, Scott E, Gomes, Wilfred, Davis, Mark C
Year of Publication 02.11.2023
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Year of Publication 02.11.2023
Patent
SCALABLE PACKAGE ARCHITECTURE USING RETICLE STITCHING AND PHOTONICS FOR ZETTA-SCALE INTEGRATED CIRCUITS
SIERS, Scott E, KOKAR, Altug, DAMARAJU, Satish, GOMES, Wilfred, DAVIS, Mark C
Year of Publication 02.11.2023
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Year of Publication 02.11.2023
Patent
LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP
Damaraju, Satish, Hsu, Steven, Agarwal, Amit, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 09.09.2021
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Year of Publication 09.09.2021
Patent
MULTIBIT VECTORED SEQUENTIAL WITH SCAN
Damaraju, Satish, Agarwal, Amit, Hsu, Steven, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 26.08.2021
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Year of Publication 26.08.2021
Patent
Multibit vectored sequential with scan
Damaraju, Satish, Agarwal, Amit, Hsu, Steven, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 18.05.2021
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Year of Publication 18.05.2021
Patent
MULTIBIT VECTORED SEQUENTIAL WITH SCAN
Damaraju, Satish, Agarwal, Amit, Hsu, Steven, Realov, Simeon, Krishnamurthy, Ram
Year of Publication 14.05.2020
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Year of Publication 14.05.2020
Patent
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS
Hsu, Steven, Agarwal, Amit, Realov, Simeon, Anders, Mark, Chen, Gregory, Kar, Monodeep, Kumar, Raghavan, Sumbul, Huseyin, Knag, Phil, Kaul, Himanshu, Suresh, Vikram, Mathew, Sanu, Rajwani, Iqbal, Damaraju, Satish, Krishnamurthy, Ram, De, Vivek
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
Published in 2020 IEEE Symposium on VLSI Circuits (01.06.2020)
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Conference Proceeding
Controlling power delivery to a processor via a bypass
Choubal, Ashish V, Jahagirdar, Sanjeev S, Islam, Rabiul, Damaraju, Satish K, Wells, Ryan D, Chen, Yun-Han, Sodhi, Inder M, Drottar, Ken, Sarurkar, Vishram
Year of Publication 27.06.2023
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Year of Publication 27.06.2023
Patent